Circuit and package design for 44GB/s inductive-coupling DRAM/SoC interface

Akira Okada; Abdul Raziz Junaidi; Yasuhiro Take; Atsutake Kosuge; Tadahiro Kuroda

doi:10.1109/ASPDAC.2015.7058978

Circuit and package design for 44GB/s inductive-coupling DRAM/SoC interface

Akira Okada, Abdul Raziz Junaidi, Yasuhiro Take, Atsutake Kosuge, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A 44GB/s inductive-coupling DRAM/SoC interface is developed by PoP integration. It utilizes the advantages of both TSV and LPDDR by using a ThruChip Interface (TCI) and an ultra-thin fan-out wafer level package (UT-FOWLP). The TCI allows data communication between the stacked chips while the UT-FOWLP thins the chips stacking distance and provides the chips with power. This proposed DRAM/SoC interface outperforms WIO2 with TSV in terms of area efficiency (4× better), immunity from simultaneous switching output (SSO) noise (32× better) and manufacturing cost (40% cheaper). In addition, it outperforms LPDDR4 in PoP in terms of power dissipation (5× lower) and timing control easiness. The inductive-coupling interface is newly designed to allow 12× improvement on its area efficiency. By using overlapping coils with quadrature phase division multiplexing (PDM), the coil density is increased by 4 times. The coil density is further increased by 3 times by shortening communication distance with the UT-FOWLP.

Original language	English
Title of host publication	20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	44-45
Number of pages	2
ISBN (Electronic)	9781479977925
DOIs	https://doi.org/10.1109/ASPDAC.2015.7058978
Publication status	Published - 2015 Mar 11
Event	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan Duration: 2015 Jan 19 → 2015 Jan 22

Publication series

Name	20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

Other

Other	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Country/Territory	Japan
City	Chiba
Period	15/1/19 → 15/1/22

ASJC Scopus subject areas

Computer Science Applications
Electrical and Electronic Engineering
Control and Systems Engineering
Modelling and Simulation

Access to Document

10.1109/ASPDAC.2015.7058978

Cite this

Okada, A., Raziz Junaidi, A., Take, Y., Kosuge, A., & Kuroda, T. (2015). Circuit and package design for 44GB/s inductive-coupling DRAM/SoC interface. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 (pp. 44-45). Article 7058978 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2015.7058978

Circuit and package design for 44GB/s inductive-coupling DRAM/SoC interface. / Okada, Akira; Raziz Junaidi, Abdul; Take, Yasuhiro et al.
20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 44-45 7058978 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Okada, A, Raziz Junaidi, A, Take, Y, Kosuge, A & Kuroda, T 2015, Circuit and package design for 44GB/s inductive-coupling DRAM/SoC interface. in 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015., 7058978, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Institute of Electrical and Electronics Engineers Inc., pp. 44-45, 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, 15/1/19. https://doi.org/10.1109/ASPDAC.2015.7058978

Okada A, Raziz Junaidi A, Take Y, Kosuge A, Kuroda T. Circuit and package design for 44GB/s inductive-coupling DRAM/SoC interface. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 44-45. 7058978. (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). doi: 10.1109/ASPDAC.2015.7058978

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abstract = "A 44GB/s inductive-coupling DRAM/SoC interface is developed by PoP integration. It utilizes the advantages of both TSV and LPDDR by using a ThruChip Interface (TCI) and an ultra-thin fan-out wafer level package (UT-FOWLP). The TCI allows data communication between the stacked chips while the UT-FOWLP thins the chips stacking distance and provides the chips with power. This proposed DRAM/SoC interface outperforms WIO2 with TSV in terms of area efficiency (4× better), immunity from simultaneous switching output (SSO) noise (32× better) and manufacturing cost (40% cheaper). In addition, it outperforms LPDDR4 in PoP in terms of power dissipation (5× lower) and timing control easiness. The inductive-coupling interface is newly designed to allow 12× improvement on its area efficiency. By using overlapping coils with quadrature phase division multiplexing (PDM), the coil density is increased by 4 times. The coil density is further increased by 3 times by shortening communication distance with the UT-FOWLP.",

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N2 - A 44GB/s inductive-coupling DRAM/SoC interface is developed by PoP integration. It utilizes the advantages of both TSV and LPDDR by using a ThruChip Interface (TCI) and an ultra-thin fan-out wafer level package (UT-FOWLP). The TCI allows data communication between the stacked chips while the UT-FOWLP thins the chips stacking distance and provides the chips with power. This proposed DRAM/SoC interface outperforms WIO2 with TSV in terms of area efficiency (4× better), immunity from simultaneous switching output (SSO) noise (32× better) and manufacturing cost (40% cheaper). In addition, it outperforms LPDDR4 in PoP in terms of power dissipation (5× lower) and timing control easiness. The inductive-coupling interface is newly designed to allow 12× improvement on its area efficiency. By using overlapping coils with quadrature phase division multiplexing (PDM), the coil density is increased by 4 times. The coil density is further increased by 3 times by shortening communication distance with the UT-FOWLP.

AB - A 44GB/s inductive-coupling DRAM/SoC interface is developed by PoP integration. It utilizes the advantages of both TSV and LPDDR by using a ThruChip Interface (TCI) and an ultra-thin fan-out wafer level package (UT-FOWLP). The TCI allows data communication between the stacked chips while the UT-FOWLP thins the chips stacking distance and provides the chips with power. This proposed DRAM/SoC interface outperforms WIO2 with TSV in terms of area efficiency (4× better), immunity from simultaneous switching output (SSO) noise (32× better) and manufacturing cost (40% cheaper). In addition, it outperforms LPDDR4 in PoP in terms of power dissipation (5× lower) and timing control easiness. The inductive-coupling interface is newly designed to allow 12× improvement on its area efficiency. By using overlapping coils with quadrature phase division multiplexing (PDM), the coil density is increased by 4 times. The coil density is further increased by 3 times by shortening communication distance with the UT-FOWLP.

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Circuit and package design for 44GB/s inductive-coupling DRAM/SoC interface

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