Circuit design for 2 Gbit/s Si bipolar crosspoint switch LSIs

Masao Suzuki; Naoaki Yamanaka; Michihiro Hirata; Shiro Kikuchi

Circuit design for 2 Gbit/s Si bipolar crosspoint switch LSIs

Masao Suzuki, Naoaki Yamanaka, Michihiro Hirata, Shiro Kikuchi

Research output: Contribution to conference › Paper › peer-review

Abstract

An Si bipolar circuit technology for gigabit-per-second crosspoint switch LSIs is described. A novel circuit design and a super-self-aligned process technology were adopted, and 8 × 8 and 16 × 16 (+16) crosspoint switch LSIs were fabricated. The LSIs successfully switched with a bit error rate of less than 10^-9 at 2.5 Gb/s using a 2⁹-1 pseudorandom NRZ sequence. Pulse jitters are made less than 76 ps at 2 Gb/s by utilizing a small internal voltage swing (225 mV) with a differential CML. The LSIs have full emitter-coupled logic (ECL)-compatible interfaces, -4/-2-V power supply voltages, and a power consumption of less than 0.9 W for an 8 × 8 LSI, and 2.8 W for a 16 × 16 (+16) LSI. These results confirm that the proposed technologies are applicable to future B-ISDN (broadband integrated services digital network) communication systems.

Original language	English
Pages	65-66
Number of pages	2
Publication status	Published - 1989 Dec 1
Externally published	Yes
Event	Symposium on VLSI Circuits 1989 - Kyoto, Japan Duration: 1989 May 25 → 1989 May 27

Other

Other	Symposium on VLSI Circuits 1989
City	Kyoto, Japan
Period	89/5/25 → 89/5/27

ASJC Scopus subject areas

Engineering(all)

Cite this

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title = "Circuit design for 2 Gbit/s Si bipolar crosspoint switch LSIs",

abstract = "An Si bipolar circuit technology for gigabit-per-second crosspoint switch LSIs is described. A novel circuit design and a super-self-aligned process technology were adopted, and 8 × 8 and 16 × 16 (+16) crosspoint switch LSIs were fabricated. The LSIs successfully switched with a bit error rate of less than 10-9 at 2.5 Gb/s using a 29-1 pseudorandom NRZ sequence. Pulse jitters are made less than 76 ps at 2 Gb/s by utilizing a small internal voltage swing (225 mV) with a differential CML. The LSIs have full emitter-coupled logic (ECL)-compatible interfaces, -4/-2-V power supply voltages, and a power consumption of less than 0.9 W for an 8 × 8 LSI, and 2.8 W for a 16 × 16 (+16) LSI. These results confirm that the proposed technologies are applicable to future B-ISDN (broadband integrated services digital network) communication systems.",

author = "Masao Suzuki and Naoaki Yamanaka and Michihiro Hirata and Shiro Kikuchi",

year = "1989",

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language = "English",

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note = "Symposium on VLSI Circuits 1989 ; Conference date: 25-05-1989 Through 27-05-1989",

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TY - CONF

T1 - Circuit design for 2 Gbit/s Si bipolar crosspoint switch LSIs

AU - Suzuki, Masao

AU - Yamanaka, Naoaki

AU - Hirata, Michihiro

AU - Kikuchi, Shiro

PY - 1989/12/1

Y1 - 1989/12/1

N2 - An Si bipolar circuit technology for gigabit-per-second crosspoint switch LSIs is described. A novel circuit design and a super-self-aligned process technology were adopted, and 8 × 8 and 16 × 16 (+16) crosspoint switch LSIs were fabricated. The LSIs successfully switched with a bit error rate of less than 10-9 at 2.5 Gb/s using a 29-1 pseudorandom NRZ sequence. Pulse jitters are made less than 76 ps at 2 Gb/s by utilizing a small internal voltage swing (225 mV) with a differential CML. The LSIs have full emitter-coupled logic (ECL)-compatible interfaces, -4/-2-V power supply voltages, and a power consumption of less than 0.9 W for an 8 × 8 LSI, and 2.8 W for a 16 × 16 (+16) LSI. These results confirm that the proposed technologies are applicable to future B-ISDN (broadband integrated services digital network) communication systems.

AB - An Si bipolar circuit technology for gigabit-per-second crosspoint switch LSIs is described. A novel circuit design and a super-self-aligned process technology were adopted, and 8 × 8 and 16 × 16 (+16) crosspoint switch LSIs were fabricated. The LSIs successfully switched with a bit error rate of less than 10-9 at 2.5 Gb/s using a 29-1 pseudorandom NRZ sequence. Pulse jitters are made less than 76 ps at 2 Gb/s by utilizing a small internal voltage swing (225 mV) with a differential CML. The LSIs have full emitter-coupled logic (ECL)-compatible interfaces, -4/-2-V power supply voltages, and a power consumption of less than 0.9 W for an 8 × 8 LSI, and 2.8 W for a 16 × 16 (+16) LSI. These results confirm that the proposed technologies are applicable to future B-ISDN (broadband integrated services digital network) communication systems.

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T2 - Symposium on VLSI Circuits 1989

Y2 - 25 May 1989 through 27 May 1989

ER -

Circuit design for 2 Gbit/s Si bipolar crosspoint switch LSIs

Abstract

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