CMOS power dissipation has been increasing due to the increase in power density. The power dissipation increased fourfold every three years until the early 1990's, due to a constant voltage scaling. Recently, a constant field scaling has been applied to reduce power dissipation, where the power density is increased proportional to the 0.7th power of scaling factor, resulting in power increase by twice every 6.5 years. It is considered that the power dissipation of CMOS chips will steadily be increased as a natural result of device scaling. Technology scaling will become difficult due to the power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.
|Title of host publication
|2001 International Microprocesses and Nanotechnology Conference, MNC 2001
|Institute of Electrical and Electronics Engineers Inc.
|Number of pages
|Published - 2001
|International Microprocesses and Nanotechnology Conference, MNC 2001 - Shimane, Japan
Duration: 2001 Oct 31 → 2001 Nov 2
|International Microprocesses and Nanotechnology Conference, MNC 2001
|01/10/31 → 01/11/2
ASJC Scopus subject areas
- Fluid Flow and Transfer Processes
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials