Design and analysis for ThruChip design for manufacturing (DFM)

Li Chung Hsu; Yasuhiro Take; Atsutake Kosuge; So Hasegawa; Junichiro Kadamoto; Tadahiro Kuroda

doi:10.1109/ASPDAC.2015.7058979

Design and analysis for ThruChip design for manufacturing (DFM)

Li Chung Hsu, Yasuhiro Take, Atsutake Kosuge, So Hasegawa, Junichiro Kadamoto, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

A 1GB/s ThruChip interface (TCI) test chip for wafer thinning, power mesh, and dummy metal fill impacts are analyzed and evaluated with test chip measurement and field solver simulation. The measurement results show that TCI coil dimension can be sized down as wafer thinning by following D/Z=3 rule. However, the experiment shows 20% power reduction by enlarging TCI coil (D/Z=6). The power mesh lies between TCI coils can dramatically decrease the TCI magnetic pulse strength and hence cause TCI to fail. Dummy metal within TCI coils has no impact on TCI transmission

Original language	English
Title of host publication	20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	46-47
Number of pages	2
ISBN (Electronic)	9781479977925
DOIs	https://doi.org/10.1109/ASPDAC.2015.7058979
Publication status	Published - 2015 Mar 11
Externally published	Yes
Event	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan Duration: 2015 Jan 19 → 2015 Jan 22

Publication series

Name	20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

Other

Other	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Country/Territory	Japan
City	Chiba
Period	15/1/19 → 15/1/22

ASJC Scopus subject areas

Computer Science Applications
Electrical and Electronic Engineering
Control and Systems Engineering
Modelling and Simulation

Access to Document

10.1109/ASPDAC.2015.7058979

Cite this

Hsu, L. C., Take, Y., Kosuge, A., Hasegawa, S., Kadamoto, J., & Kuroda, T. (2015). Design and analysis for ThruChip design for manufacturing (DFM). In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 (pp. 46-47). Article 7058979 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2015.7058979

Design and analysis for ThruChip design for manufacturing (DFM). / Hsu, Li Chung; Take, Yasuhiro; Kosuge, Atsutake et al.
20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 46-47 7058979 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hsu, LC, Take, Y, Kosuge, A, Hasegawa, S, Kadamoto, J & Kuroda, T 2015, Design and analysis for ThruChip design for manufacturing (DFM). in 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015., 7058979, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Institute of Electrical and Electronics Engineers Inc., pp. 46-47, 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, 15/1/19. https://doi.org/10.1109/ASPDAC.2015.7058979

Hsu LC, Take Y, Kosuge A, Hasegawa S, Kadamoto J, Kuroda T. Design and analysis for ThruChip design for manufacturing (DFM). In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 46-47. 7058979. (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). doi: 10.1109/ASPDAC.2015.7058979

@inproceedings{187b3957363f4b9d8d5bf3a8ed0975c7,

title = "Design and analysis for ThruChip design for manufacturing (DFM)",

abstract = "A 1GB/s ThruChip interface (TCI) test chip for wafer thinning, power mesh, and dummy metal fill impacts are analyzed and evaluated with test chip measurement and field solver simulation. The measurement results show that TCI coil dimension can be sized down as wafer thinning by following D/Z=3 rule. However, the experiment shows 20% power reduction by enlarging TCI coil (D/Z=6). The power mesh lies between TCI coils can dramatically decrease the TCI magnetic pulse strength and hence cause TCI to fail. Dummy metal within TCI coils has no impact on TCI transmission",

author = "Hsu, {Li Chung} and Yasuhiro Take and Atsutake Kosuge and So Hasegawa and Junichiro Kadamoto and Tadahiro Kuroda",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 ; Conference date: 19-01-2015 Through 22-01-2015",

year = "2015",

month = mar,

day = "11",

doi = "10.1109/ASPDAC.2015.7058979",

language = "English",

series = "20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "46--47",

booktitle = "20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015",

}

TY - GEN

T1 - Design and analysis for ThruChip design for manufacturing (DFM)

AU - Hsu, Li Chung

AU - Take, Yasuhiro

AU - Kosuge, Atsutake

AU - Hasegawa, So

AU - Kadamoto, Junichiro

AU - Kuroda, Tadahiro

PY - 2015/3/11

Y1 - 2015/3/11

N2 - A 1GB/s ThruChip interface (TCI) test chip for wafer thinning, power mesh, and dummy metal fill impacts are analyzed and evaluated with test chip measurement and field solver simulation. The measurement results show that TCI coil dimension can be sized down as wafer thinning by following D/Z=3 rule. However, the experiment shows 20% power reduction by enlarging TCI coil (D/Z=6). The power mesh lies between TCI coils can dramatically decrease the TCI magnetic pulse strength and hence cause TCI to fail. Dummy metal within TCI coils has no impact on TCI transmission

AB - A 1GB/s ThruChip interface (TCI) test chip for wafer thinning, power mesh, and dummy metal fill impacts are analyzed and evaluated with test chip measurement and field solver simulation. The measurement results show that TCI coil dimension can be sized down as wafer thinning by following D/Z=3 rule. However, the experiment shows 20% power reduction by enlarging TCI coil (D/Z=6). The power mesh lies between TCI coils can dramatically decrease the TCI magnetic pulse strength and hence cause TCI to fail. Dummy metal within TCI coils has no impact on TCI transmission

UR - http://www.scopus.com/inward/record.url?scp=84926459227&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84926459227&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2015.7058979

DO - 10.1109/ASPDAC.2015.7058979

M3 - Conference contribution

AN - SCOPUS:84926459227

T3 - 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

SP - 46

EP - 47

BT - 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

Y2 - 19 January 2015 through 22 January 2015

ER -

Design and analysis for ThruChip design for manufacturing (DFM)

Abstract

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