Design and evaluation of high performance microprocessor with reconfigurable on-chip memory

T. Ohneda; M. Kondo; M. Imai; H. Nakamura

doi:10.1109/APCCAS.2002.1114939

Design and evaluation of high performance microprocessor with reconfigurable on-chip memory

T. Ohneda, M. Kondo, M. Imai, H. Nakamura

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

The performance gap between processor and main memory is serious problem especially in high performance computing. In order to overcome this problem, we have proposed a new processor architecture called SCIMA, which integrates software-controllable memory (SCM) into a processor chip as a part of main memory in addition to ordinary cache. SCIMA is defined as an extension of a general microprocessor whose load/store unit is extended to control data accesses to the SCM. In this paper, we present a load/store unit of SCIMA by extending the unit of MIPS R10000 processor and evaluate the impact of the extension on area and clock frequency. The evaluation results reveal that SCIMA achieves 1.5 - 10 times higher performance compared with cache based architecture although the cycle time of SCIMA is 5.7% longer.

Original language	English
Title of host publication	Proceedings - APCCAS 2002
Subtitle of host publication	Asia-Pacific Conference on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	211-216
Number of pages	6
ISBN (Electronic)	0780376900
DOIs	https://doi.org/10.1109/APCCAS.2002.1114939
Publication status	Published - 2002
Externally published	Yes
Event	Asia-Pacific Conference on Circuits and Systems, APCCAS 2002 - Denpasar, Bali, Indonesia Duration: 2002 Oct 28 → 2002 Oct 31

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Volume	1

Other

Other	Asia-Pacific Conference on Circuits and Systems, APCCAS 2002
Country/Territory	Indonesia
City	Denpasar, Bali
Period	02/10/28 → 02/10/31

Keywords

Clocks
Computer architecture
Delay
Educational programs
Frequency
High performance computing
Memory architecture
Microprocessors
Prefetching
Throughput

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/APCCAS.2002.1114939

Cite this

Ohneda, T., Kondo, M., Imai, M., & Nakamura, H. (2002). Design and evaluation of high performance microprocessor with reconfigurable on-chip memory. In Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems (pp. 211-216). Article 1114939 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; Vol. 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2002.1114939

Design and evaluation of high performance microprocessor with reconfigurable on-chip memory. / Ohneda, T.; Kondo, M.; Imai, M. et al.
Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2002. p. 211-216 1114939 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ohneda, T, Kondo, M, Imai, M & Nakamura, H 2002, Design and evaluation of high performance microprocessor with reconfigurable on-chip memory. in Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems., 1114939, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, vol. 1, Institute of Electrical and Electronics Engineers Inc., pp. 211-216, Asia-Pacific Conference on Circuits and Systems, APCCAS 2002, Denpasar, Bali, Indonesia, 02/10/28. https://doi.org/10.1109/APCCAS.2002.1114939

Ohneda T, Kondo M, Imai M, Nakamura H. Design and evaluation of high performance microprocessor with reconfigurable on-chip memory. In Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc. 2002. p. 211-216. 1114939. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). doi: 10.1109/APCCAS.2002.1114939

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abstract = "The performance gap between processor and main memory is serious problem especially in high performance computing. In order to overcome this problem, we have proposed a new processor architecture called SCIMA, which integrates software-controllable memory (SCM) into a processor chip as a part of main memory in addition to ordinary cache. SCIMA is defined as an extension of a general microprocessor whose load/store unit is extended to control data accesses to the SCM. In this paper, we present a load/store unit of SCIMA by extending the unit of MIPS R10000 processor and evaluate the impact of the extension on area and clock frequency. The evaluation results reveal that SCIMA achieves 1.5 - 10 times higher performance compared with cache based architecture although the cycle time of SCIMA is 5.7% longer.",

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AB - The performance gap between processor and main memory is serious problem especially in high performance computing. In order to overcome this problem, we have proposed a new processor architecture called SCIMA, which integrates software-controllable memory (SCM) into a processor chip as a part of main memory in addition to ordinary cache. SCIMA is defined as an extension of a general microprocessor whose load/store unit is extended to control data accesses to the SCM. In this paper, we present a load/store unit of SCIMA by extending the unit of MIPS R10000 processor and evaluate the impact of the extension on area and clock frequency. The evaluation results reveal that SCIMA achieves 1.5 - 10 times higher performance compared with cache based architecture although the cycle time of SCIMA is 5.7% longer.

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KW - Prefetching

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Design and evaluation of high performance microprocessor with reconfigurable on-chip memory

Abstract

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Keywords

ASJC Scopus subject areas

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