Design and evaluation of the cache coherent multistage interconnection network with temporary directory

Takashi Midorikawa, Masato Sumiyoshi, Yasuki Tanabe, Hideharu Amano

Research output: Contribution to journalArticlepeer-review


Although cache control mechanisms for use in multiprocessors that use a multistage interconnection network (MIN) as the interconnecting network have been proposed in which a directory or the cache itself is built into the switches in the MIN, the structure of the switches in these methods have been complex and there therefore remains room for improvement. Our research group has therefore proposed a MIN with directory cache switch (MINDIC) that implements cache control by only building small-capacity directory caches into the switches. This paper reports on the results of evaluating MINDIC using a clock level simulator. The results reveal that MINDIC is able to achieve a level of cache control efficiency that is equal to that of a full map directory management scheme by setting the number of entries in the MINDIC directory caches to approximately 2048 entries. The results also show that the amount of memory required for the directory can be greatly reduced by MINDIC.

Original languageEnglish
Pages (from-to)11-23
Number of pages13
JournalElectronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
Issue number9
Publication statusPublished - 2006 Sept


  • Cache coherence
  • Multiprocessor
  • Multistage interconnection network

ASJC Scopus subject areas

  • General Physics and Astronomy
  • Computer Networks and Communications
  • Electrical and Electronic Engineering


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