Design and implementation of a handshake join architecture on FPGA

Yasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, Tsutomu Yoshinaga

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


A novel design is proposed to implement highly parallel stream join operators on a field-programmable gate array (FPGA), by examining handshake join algorithm for hardware implementation. The proposed design is evaluated in terms of the hardware resource usage, the maximum clock frequency, and the performance. Experimental results indicate that the proposed implementation can handle considerably high input rates, especially at low match rates. Results of simulation conducted to optimize size of buffers included in join and merge units give a new intuition regarding static and adaptive buffer tuning in handshake join.

Original languageEnglish
Pages (from-to)2919-2927
Number of pages9
JournalIEICE Transactions on Information and Systems
Issue number12
Publication statusPublished - 2012 Dec
Externally publishedYes


  • Accelerator
  • Data stream processing
  • FPGA
  • Handshake join
  • Window join operator

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence


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