Design automation methodology of a critical path monitor for adaptive voltage controls

Ryosuke Kazami; Hayate Okuhara; Hideharu Amano

doi:10.1109/CoolChips.2018.8373073

Design automation methodology of a critical path monitor for adaptive voltage controls

Ryosuke Kazami, Hayate Okuhara, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

The development of recent CMOS technologies such as Fully Depleted Silicon on Insulator (FD-SOI) allows VLSI systems to operate with lower power than the conventional bulk transistors [1, 2]. Thanks to its high degree of noise immunity, low power supply voltages (V_DD) can be applied to the FD-SOI devices. Also, since the effect of body biasing is further endorsed in such devices, adaptive voltage control for both power supply voltage and body bias voltages (V_BN for nMOS and V_BP for pMOS) can be aggressively used.

Original language	English
Title of host publication	21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-3
Number of pages	3
ISBN (Electronic)	9781538661024
DOIs	https://doi.org/10.1109/CoolChips.2018.8373073
Publication status	Published - 2018 Jun 5
Event	21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Yokohama, Japan Duration: 2018 Apr 18 → 2018 Apr 20

Publication series

Name	21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings

Other

Other	21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018
Country/Territory	Japan
City	Yokohama
Period	18/4/18 → 18/4/20

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/CoolChips.2018.8373073

Cite this

Kazami, R., Okuhara, H., & Amano, H. (2018). Design automation methodology of a critical path monitor for adaptive voltage controls. In 21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings (pp. 1-3). (21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CoolChips.2018.8373073

Design automation methodology of a critical path monitor for adaptive voltage controls. / Kazami, Ryosuke; Okuhara, Hayate; Amano, Hideharu.
21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-3 (21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kazami, R, Okuhara, H & Amano, H 2018, Design automation methodology of a critical path monitor for adaptive voltage controls. in 21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings. 21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 1-3, 21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018, Yokohama, Japan, 18/4/18. https://doi.org/10.1109/CoolChips.2018.8373073

Kazami R, Okuhara H, Amano H. Design automation methodology of a critical path monitor for adaptive voltage controls. In 21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-3. (21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings). doi: 10.1109/CoolChips.2018.8373073

Kazami, Ryosuke ; Okuhara, Hayate ; Amano, Hideharu. / Design automation methodology of a critical path monitor for adaptive voltage controls. 21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1-3 (21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings).

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abstract = "The development of recent CMOS technologies such as Fully Depleted Silicon on Insulator (FD-SOI) allows VLSI systems to operate with lower power than the conventional bulk transistors [1, 2]. Thanks to its high degree of noise immunity, low power supply voltages (VDD) can be applied to the FD-SOI devices. Also, since the effect of body biasing is further endorsed in such devices, adaptive voltage control for both power supply voltage and body bias voltages (VBN for nMOS and VBP for pMOS) can be aggressively used.",

author = "Ryosuke Kazami and Hayate Okuhara and Hideharu Amano",

note = "Funding Information: This work was supported by JSPS KAKENHI S Grant Number 25220002. The device model of SOTB in this study has been provided by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Renesas Electronics Corp. The authors also thank Synopsys Inc. for the EDA tools support. Publisher Copyright: {\textcopyright} 2018 IEEE.; 21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 ; Conference date: 18-04-2018 Through 20-04-2018",

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AB - The development of recent CMOS technologies such as Fully Depleted Silicon on Insulator (FD-SOI) allows VLSI systems to operate with lower power than the conventional bulk transistors [1, 2]. Thanks to its high degree of noise immunity, low power supply voltages (VDD) can be applied to the FD-SOI devices. Also, since the effect of body biasing is further endorsed in such devices, adaptive voltage control for both power supply voltage and body bias voltages (VBN for nMOS and VBP for pMOS) can be aggressively used.

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Design automation methodology of a critical path monitor for adaptive voltage controls

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