Design methodology and trade-offs analysis for parameterized dynamically reconfigurable processor arrays

Yohei Hasegawa; Satoshi Tsutsumi; Vasutan Tanbunheng; Takuro Nakamura; Takashi Nishimura; Hideharu Amano

doi:10.1109/FPL.2007.4380771

Design methodology and trade-offs analysis for parameterized dynamically reconfigurable processor arrays

Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tanbunheng, Takuro Nakamura, Takashi Nishimura, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

In this paper, we propose a Dynamically Reconfigurable Processor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully parameterized. By specifying architectural parameters, it can automatically generate RTL model, simulation environment, and finally chip layout. In our DRPA generator, although the fundamental design of a processing element (PE) and an inter-PE connection is fixed, the array size, PE granularity, and connection flexibilities of intra/inter PE are selectable. In this paper, we have generated various types of DRPAs and evaluated semiconductor area and speed by using the AS-PLA/STARC 90-nm CMOS technology. From evaluation results, fundamental trade-offs between architectural parameters and area/delay are analyzed.

Original language	English
Title of host publication	Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL
Pages	796-799
Number of pages	4
DOIs	https://doi.org/10.1109/FPL.2007.4380771
Publication status	Published - 2007
Event	2007 International Conference on Field Programmable Logic and Applications, FPL - Amsterdam, Netherlands Duration: 2007 Aug 27 → 2007 Aug 29

Publication series

Name	Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

Other

Other	2007 International Conference on Field Programmable Logic and Applications, FPL
Country/Territory	Netherlands
City	Amsterdam
Period	07/8/27 → 07/8/29

ASJC Scopus subject areas

Computer Science Applications
Electrical and Electronic Engineering

Access to Document

10.1109/FPL.2007.4380771

Cite this

Hasegawa, Y., Tsutsumi, S., Tanbunheng, V., Nakamura, T., Nishimura, T., & Amano, H. (2007). Design methodology and trade-offs analysis for parameterized dynamically reconfigurable processor arrays. In Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL (pp. 796-799). Article 4380771 (Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL). https://doi.org/10.1109/FPL.2007.4380771

Design methodology and trade-offs analysis for parameterized dynamically reconfigurable processor arrays. / Hasegawa, Yohei; Tsutsumi, Satoshi; Tanbunheng, Vasutan et al.
Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. 2007. p. 796-799 4380771 (Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hasegawa, Y, Tsutsumi, S, Tanbunheng, V, Nakamura, T, Nishimura, T & Amano, H 2007, Design methodology and trade-offs analysis for parameterized dynamically reconfigurable processor arrays. in Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL., 4380771, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL, pp. 796-799, 2007 International Conference on Field Programmable Logic and Applications, FPL, Amsterdam, Netherlands, 07/8/27. https://doi.org/10.1109/FPL.2007.4380771

Hasegawa Y, Tsutsumi S, Tanbunheng V, Nakamura T, Nishimura T, Amano H. Design methodology and trade-offs analysis for parameterized dynamically reconfigurable processor arrays. In Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. 2007. p. 796-799. 4380771. (Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL). doi: 10.1109/FPL.2007.4380771

Hasegawa, Yohei ; Tsutsumi, Satoshi ; Tanbunheng, Vasutan et al. / Design methodology and trade-offs analysis for parameterized dynamically reconfigurable processor arrays. Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. 2007. pp. 796-799 (Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL).

@inproceedings{707159fde2194a9d9ca5c65028dcbca3,

title = "Design methodology and trade-offs analysis for parameterized dynamically reconfigurable processor arrays",

abstract = "In this paper, we propose a Dynamically Reconfigurable Processor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully parameterized. By specifying architectural parameters, it can automatically generate RTL model, simulation environment, and finally chip layout. In our DRPA generator, although the fundamental design of a processing element (PE) and an inter-PE connection is fixed, the array size, PE granularity, and connection flexibilities of intra/inter PE are selectable. In this paper, we have generated various types of DRPAs and evaluated semiconductor area and speed by using the AS-PLA/STARC 90-nm CMOS technology. From evaluation results, fundamental trade-offs between architectural parameters and area/delay are analyzed.",

author = "Yohei Hasegawa and Satoshi Tsutsumi and Vasutan Tanbunheng and Takuro Nakamura and Takashi Nishimura and Hideharu Amano",

year = "2007",

doi = "10.1109/FPL.2007.4380771",

language = "English",

isbn = "1424410606",

series = "Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL",

pages = "796--799",

booktitle = "Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL",

note = "2007 International Conference on Field Programmable Logic and Applications, FPL ; Conference date: 27-08-2007 Through 29-08-2007",

}

TY - GEN

T1 - Design methodology and trade-offs analysis for parameterized dynamically reconfigurable processor arrays

AU - Hasegawa, Yohei

AU - Tsutsumi, Satoshi

AU - Tanbunheng, Vasutan

AU - Nakamura, Takuro

AU - Nishimura, Takashi

AU - Amano, Hideharu

PY - 2007

Y1 - 2007

N2 - In this paper, we propose a Dynamically Reconfigurable Processor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully parameterized. By specifying architectural parameters, it can automatically generate RTL model, simulation environment, and finally chip layout. In our DRPA generator, although the fundamental design of a processing element (PE) and an inter-PE connection is fixed, the array size, PE granularity, and connection flexibilities of intra/inter PE are selectable. In this paper, we have generated various types of DRPAs and evaluated semiconductor area and speed by using the AS-PLA/STARC 90-nm CMOS technology. From evaluation results, fundamental trade-offs between architectural parameters and area/delay are analyzed.

AB - In this paper, we propose a Dynamically Reconfigurable Processor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully parameterized. By specifying architectural parameters, it can automatically generate RTL model, simulation environment, and finally chip layout. In our DRPA generator, although the fundamental design of a processing element (PE) and an inter-PE connection is fixed, the array size, PE granularity, and connection flexibilities of intra/inter PE are selectable. In this paper, we have generated various types of DRPAs and evaluated semiconductor area and speed by using the AS-PLA/STARC 90-nm CMOS technology. From evaluation results, fundamental trade-offs between architectural parameters and area/delay are analyzed.

UR - http://www.scopus.com/inward/record.url?scp=48149115491&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=48149115491&partnerID=8YFLogxK

U2 - 10.1109/FPL.2007.4380771

DO - 10.1109/FPL.2007.4380771

M3 - Conference contribution

AN - SCOPUS:48149115491

SN - 1424410606

SN - 9781424410606

T3 - Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

SP - 796

EP - 799

BT - Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

T2 - 2007 International Conference on Field Programmable Logic and Applications, FPL

Y2 - 27 August 2007 through 29 August 2007

ER -

Design methodology and trade-offs analysis for parameterized dynamically reconfigurable processor arrays

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this