Design of a low power NoC router using marching memory through type

Ryota Yasudo; Takahiro Kagami; Hideharu Amano; Yasunobu Nakase; Masashi Watanabe; Tsukasa Oishi; Toru Shimizu; Tadao Nakamura

doi:10.1109/NOCS.2014.7008769

Design of a low power NoC router using marching memory through type

Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

Power consumption of Network-on-Chip (NoC) is becoming more important in many core processors. Input buffers utilized in routers consume a significant part of the total power of NoCs. In order to reduce this power consumption, a novel power efficient memory called Marching Memory Through type (MMTH) is introduced. By connecting transparent latches in tandem, MMTH achieves high speed operation with a low power consumption. MMTH, however, requires a certain overhead at read operation, and hence we propose a latency reduction scheme based on the look-ahead routing. The proposed router was designed in Renesas's 40nm process and compared with a standard router using conventional register-based FIFOs in terms of the network performance, application performance, and power consumption. The result of evaluation shows that the proposed router reduces the power consumption by 42.4% on average at 2GHz and the expense of only 0.5-2.0% performance overhead.

Original language	English
Title of host publication	Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014
Editors	Davide Bertozzi, Luca Benini, Sudhakar Yalamanchili, Joerg Henkel
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	111-118
Number of pages	8
ISBN (Electronic)	9781479953479
DOIs	https://doi.org/10.1109/NOCS.2014.7008769
Publication status	Published - 2015 Jan 13
Event	8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014 - Ferrara, Italy Duration: 2014 Sept 17 → 2014 Sept 19

Publication series

Name	Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014

Other

Other	8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014
Country/Territory	Italy
City	Ferrara
Period	14/9/17 → 14/9/19

ASJC Scopus subject areas

Computer Networks and Communications
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/NOCS.2014.7008769

Cite this

Yasudo, R., Kagami, T., Amano, H., Nakase, Y., Watanabe, M., Oishi, T., Shimizu, T., & Nakamura, T. (2015). Design of a low power NoC router using marching memory through type. In D. Bertozzi, L. Benini, S. Yalamanchili, & J. Henkel (Eds.), Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014 (pp. 111-118). Article 7008769 (Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NOCS.2014.7008769

Design of a low power NoC router using marching memory through type. / Yasudo, Ryota; Kagami, Takahiro; Amano, Hideharu et al.
Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014. ed. / Davide Bertozzi; Luca Benini; Sudhakar Yalamanchili; Joerg Henkel. Institute of Electrical and Electronics Engineers Inc., 2015. p. 111-118 7008769 (Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yasudo, R, Kagami, T, Amano, H, Nakase, Y, Watanabe, M, Oishi, T, Shimizu, T & Nakamura, T 2015, Design of a low power NoC router using marching memory through type. in D Bertozzi, L Benini, S Yalamanchili & J Henkel (eds), Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014., 7008769, Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014, Institute of Electrical and Electronics Engineers Inc., pp. 111-118, 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014, Ferrara, Italy, 14/9/17. https://doi.org/10.1109/NOCS.2014.7008769

Yasudo R, Kagami T, Amano H, Nakase Y, Watanabe M, Oishi T et al. Design of a low power NoC router using marching memory through type. In Bertozzi D, Benini L, Yalamanchili S, Henkel J, editors, Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014. Institute of Electrical and Electronics Engineers Inc. 2015. p. 111-118. 7008769. (Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014). doi: 10.1109/NOCS.2014.7008769

Yasudo, Ryota ; Kagami, Takahiro ; Amano, Hideharu et al. / Design of a low power NoC router using marching memory through type. Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014. editor / Davide Bertozzi ; Luca Benini ; Sudhakar Yalamanchili ; Joerg Henkel. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 111-118 (Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014).

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Design of a low power NoC router using marching memory through type

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