Design of new logic architectures utilizing optimized suspended-gate single-electron transistors

Benjamin Pruvost; Ken Uchida; Hiroshi Mizuta; Shunri Oda

doi:10.1109/TNANO.2009.2030502

Design of new logic architectures utilizing optimized suspended-gate single-electron transistors

Benjamin Pruvost, Ken Uchida, Hiroshi Mizuta, Shunri Oda

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

The operation and performances of the suspended-gate single-electron transistor (SET) are investigated through simulation. The movable gate is 3-D optimized, so that low actuation voltage (0.4 V), fast switching (1 ns), and ultralow pull-in energy (0.015 fJ) are simulated. A two-state capacitor model based on the 3-D results is then embedded with a SET analytical model in a SPICE environment to investigate the operation of the device. Through the control of the Coulomb oscillation characteristics, the position of the movable gate enables a background charge insensitive coding of the information. New circuit architectures with applications in cellular nonlinear network and pattern matching are also proposed and simulated.

Original language	English
Article number	5223702
Pages (from-to)	504-512
Number of pages	9
Journal	IEEE Transactions on Nanotechnology
Volume	9
Issue number	4
DOIs	https://doi.org/10.1109/TNANO.2009.2030502
Publication status	Published - 2010 Jul
Externally published	Yes

Keywords

1-D and 3-D modeling
cantilever switch
movable gate
nanoelectromechanical system (NEMS)
single-electron transistor (SET)

ASJC Scopus subject areas

Computer Science Applications
Electrical and Electronic Engineering

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10.1109/TNANO.2009.2030502

Cite this

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title = "Design of new logic architectures utilizing optimized suspended-gate single-electron transistors",

abstract = "The operation and performances of the suspended-gate single-electron transistor (SET) are investigated through simulation. The movable gate is 3-D optimized, so that low actuation voltage (0.4 V), fast switching (1 ns), and ultralow pull-in energy (0.015 fJ) are simulated. A two-state capacitor model based on the 3-D results is then embedded with a SET analytical model in a SPICE environment to investigate the operation of the device. Through the control of the Coulomb oscillation characteristics, the position of the movable gate enables a background charge insensitive coding of the information. New circuit architectures with applications in cellular nonlinear network and pattern matching are also proposed and simulated.",

keywords = "1-D and 3-D modeling, cantilever switch, movable gate, nanoelectromechanical system (NEMS), single-electron transistor (SET)",

author = "Benjamin Pruvost and Ken Uchida and Hiroshi Mizuta and Shunri Oda",

year = "2010",

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AU - Uchida, Ken

AU - Mizuta, Hiroshi

AU - Oda, Shunri

PY - 2010/7

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N2 - The operation and performances of the suspended-gate single-electron transistor (SET) are investigated through simulation. The movable gate is 3-D optimized, so that low actuation voltage (0.4 V), fast switching (1 ns), and ultralow pull-in energy (0.015 fJ) are simulated. A two-state capacitor model based on the 3-D results is then embedded with a SET analytical model in a SPICE environment to investigate the operation of the device. Through the control of the Coulomb oscillation characteristics, the position of the movable gate enables a background charge insensitive coding of the information. New circuit architectures with applications in cellular nonlinear network and pattern matching are also proposed and simulated.

AB - The operation and performances of the suspended-gate single-electron transistor (SET) are investigated through simulation. The movable gate is 3-D optimized, so that low actuation voltage (0.4 V), fast switching (1 ns), and ultralow pull-in energy (0.015 fJ) are simulated. A two-state capacitor model based on the 3-D results is then embedded with a SET analytical model in a SPICE environment to investigate the operation of the device. Through the control of the Coulomb oscillation characteristics, the position of the movable gate enables a background charge insensitive coding of the information. New circuit architectures with applications in cellular nonlinear network and pattern matching are also proposed and simulated.

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KW - nanoelectromechanical system (NEMS)

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Design of new logic architectures utilizing optimized suspended-gate single-electron transistors

Abstract

Keywords

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