Development of sensitivity and offset calibratable capacitance detection CMOS IC using PLL configuration

Yoshinori Matsumoto, Miho Matsuura, G. R. Dharmasena, Makoto Ishida

Research output: Contribution to journalArticlepeer-review


A CMOS capacitance detection integrated circuit for silicon capacitive sensors has been developed using PLL configuration. The circuit is composed of two voltage controlled capacitance to frequency converters, a phase sensitive detector, a charge pump and a low pass filter. The circuit has differential configuration in order to supress the circuit power suply dependence and temperature dependence. The circuit is also desiged to be able to calibrate variations of the sensor sensitivity and offset with feedback principle. The circuit was designed with SPICE simulator and fabricated with standared CMOS technology of Toyohashi University of Technology. From the measurment result, the sensitivity and offset can be calibrated with applied bias voltage, and the power supply dependence and temperature dependence of the circuit were neally zero, The circuit is considerd as candidate of detection circuit for surface micromaching capacitve sensors.

Original languageEnglish
Pages (from-to)571-575
Number of pages5
Journalieej transactions on sensors and micromachines
Issue number11
Publication statusPublished - 1997
Externally publishedYes

ASJC Scopus subject areas

  • Mechanical Engineering
  • Electrical and Electronic Engineering


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