Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs

Toshinori Numata, Ken Uchida, Junji Koga, Shin Ichi Takagi

Research output: Contribution to conferencePaperpeer-review

16 Citations (Scopus)

Abstract

Device design issues regarding threshold voltage (Vth) control, short channel effects (SCE) and subthreshold slope are qantitatively studied for fully-depleted (FD) SOI MOSFETs under the sub-100 nm regime. As for the Vth adjustment method, the combination of back gate bias (Vg2) and gate work function (Φm) control is found to provide superior SCE, Vth fluctuation due to SOI thickness variation and current drive. As for the subthreshold slope (SS), on the other hand, the optimization of thickness and permittivity of buried oxides is a key issue. It is found that, when the gate length is less than 100 nm, SS has a minimum value at buried oxide thickness of around 40 nm, irrespective of SOI thickness. It is also shown that the reduction in the permittivity of buried oxides improves SS.

Original languageEnglish
Pages179-180
Number of pages2
DOIs
Publication statusPublished - 2002
Externally publishedYes
EventIEEE International SOI Conference - Williamsburg, VA, United States
Duration: 2002 Oct 72002 Oct 10

Other

OtherIEEE International SOI Conference
Country/TerritoryUnited States
CityWilliamsburg, VA
Period02/10/702/10/10

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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