Digital embedded memory scheme using voltage scaling and body bias separation for low-power system

Yusuke Yoshida; Kimiyoshi Usami; Hideharu Amano

doi:10.1109/ISOCC.2017.8368840

Digital embedded memory scheme using voltage scaling and body bias separation for low-power system

Yusuke Yoshida, Kimiyoshi Usami, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Standard Cell based Memory (SCM) is drawing attention as a technique to use the standard digital design flow to realize embedded memory macros. One of the strong points of SCM is that it correctly operates at such low voltage that SRAM macros provided by vendors usually do not work. This paper describes a design of energy-efficient SCM using Silicon-on-Thin-BOX (SOTB). We present automatic layout methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Results from simulations and chip measurements have demonstrated effectiveness of this approach.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2017, ISOCC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	148-149
Number of pages	2
ISBN (Electronic)	9781538622858
DOIs	https://doi.org/10.1109/ISOCC.2017.8368840
Publication status	Published - 2018 May 29
Event	14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of Duration: 2017 Nov 5 → 2017 Nov 8

Other

Other	14th International SoC Design Conference, ISOCC 2017
Country/Territory	Korea, Republic of
City	Seoul
Period	17/11/5 → 17/11/8

Keywords

Body bias control
Low-power
Silicon-on-Thin-BOX (SOTB)
Standard cell memory
Ultra-low voltage

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ISOCC.2017.8368840

Cite this

Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. / Yoshida, Yusuke; Usami, Kimiyoshi; Amano, Hideharu.
Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 148-149.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yoshida, Y, Usami, K & Amano, H 2018, Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. in Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., pp. 148-149, 14th International SoC Design Conference, ISOCC 2017, Seoul, Korea, Republic of, 17/11/5. https://doi.org/10.1109/ISOCC.2017.8368840

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title = "Digital embedded memory scheme using voltage scaling and body bias separation for low-power system",

abstract = "Standard Cell based Memory (SCM) is drawing attention as a technique to use the standard digital design flow to realize embedded memory macros. One of the strong points of SCM is that it correctly operates at such low voltage that SRAM macros provided by vendors usually do not work. This paper describes a design of energy-efficient SCM using Silicon-on-Thin-BOX (SOTB). We present automatic layout methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Results from simulations and chip measurements have demonstrated effectiveness of this approach.",

keywords = "Body bias control, Low-power, Silicon-on-Thin-BOX (SOTB), Standard cell memory, Ultra-low voltage",

author = "Yusuke Yoshida and Kimiyoshi Usami and Hideharu Amano",

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doi = "10.1109/ISOCC.2017.8368840",

language = "English",

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booktitle = "Proceedings - International SoC Design Conference 2017, ISOCC 2017",

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AU - Yoshida, Yusuke

AU - Usami, Kimiyoshi

AU - Amano, Hideharu

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N2 - Standard Cell based Memory (SCM) is drawing attention as a technique to use the standard digital design flow to realize embedded memory macros. One of the strong points of SCM is that it correctly operates at such low voltage that SRAM macros provided by vendors usually do not work. This paper describes a design of energy-efficient SCM using Silicon-on-Thin-BOX (SOTB). We present automatic layout methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Results from simulations and chip measurements have demonstrated effectiveness of this approach.

AB - Standard Cell based Memory (SCM) is drawing attention as a technique to use the standard digital design flow to realize embedded memory macros. One of the strong points of SCM is that it correctly operates at such low voltage that SRAM macros provided by vendors usually do not work. This paper describes a design of energy-efficient SCM using Silicon-on-Thin-BOX (SOTB). We present automatic layout methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Results from simulations and chip measurements have demonstrated effectiveness of this approach.

KW - Body bias control

KW - Low-power

KW - Silicon-on-Thin-BOX (SOTB)

KW - Standard cell memory

KW - Ultra-low voltage

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BT - Proceedings - International SoC Design Conference 2017, ISOCC 2017

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Digital embedded memory scheme using voltage scaling and body bias separation for low-power system

Abstract

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Keywords

ASJC Scopus subject areas

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