EFFECTS OF P-TYPE BARRIER LAYER ON CHARACTERISTICS OF SUB-MICRON GATE SELF-ALIGNED GaAs FET.

K. Matsumoto; N. Hashizume; N. Atoda; Y. Awano

EFFECTS OF P-TYPE BARRIER LAYER ON CHARACTERISTICS OF SUB-MICRON GATE SELF-ALIGNED GaAs FET.

K. Matsumoto
, N. Hashizume
, N. Atoda
, Y. Awano

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The substrate current under the channel layer in a sub-micron gate self-aligned GaAs FET is shown by Monte Carlo simulation to be the major cause of the short channel effects. By introducing a p-type layer between the channel layer and the substrate, the short channel effects of the FETs having sub-micron gate length are suppressed significantly.

Original language	English
Title of host publication	Institute of Physics Conference Series
Editors	B. de Cremoux
Pages	515-520
Number of pages	6
Edition	74
Publication status	Published - 1985 Dec 1
Externally published	Yes

Publication series

Name	Institute of Physics Conference Series
Number	74
ISSN (Print)	0373-0751

ASJC Scopus subject areas

General Physics and Astronomy

Cite this

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title = "EFFECTS OF P-TYPE BARRIER LAYER ON CHARACTERISTICS OF SUB-MICRON GATE SELF-ALIGNED GaAs FET.",

abstract = "The substrate current under the channel layer in a sub-micron gate self-aligned GaAs FET is shown by Monte Carlo simulation to be the major cause of the short channel effects. By introducing a p-type layer between the channel layer and the substrate, the short channel effects of the FETs having sub-micron gate length are suppressed significantly.",

author = "K. Matsumoto and N. Hashizume and N. Atoda and Y. Awano",

year = "1985",

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day = "1",

language = "English",

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series = "Institute of Physics Conference Series",

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T1 - EFFECTS OF P-TYPE BARRIER LAYER ON CHARACTERISTICS OF SUB-MICRON GATE SELF-ALIGNED GaAs FET.

AU - Matsumoto, K.

AU - Hashizume, N.

AU - Atoda, N.

AU - Awano, Y.

PY - 1985/12/1

Y1 - 1985/12/1

N2 - The substrate current under the channel layer in a sub-micron gate self-aligned GaAs FET is shown by Monte Carlo simulation to be the major cause of the short channel effects. By introducing a p-type layer between the channel layer and the substrate, the short channel effects of the FETs having sub-micron gate length are suppressed significantly.

AB - The substrate current under the channel layer in a sub-micron gate self-aligned GaAs FET is shown by Monte Carlo simulation to be the major cause of the short channel effects. By introducing a p-type layer between the channel layer and the substrate, the short channel effects of the FETs having sub-micron gate length are suppressed significantly.

UR - https://www.scopus.com/pages/publications/0022187518

UR - https://www.scopus.com/pages/publications/0022187518#tab=citedBy

M3 - Conference contribution

AN - SCOPUS:0022187518

SN - 0854981659

T3 - Institute of Physics Conference Series

SP - 515

EP - 520

BT - Institute of Physics Conference Series

A2 - de Cremoux, B.

ER -

EFFECTS OF P-TYPE BARRIER LAYER ON CHARACTERISTICS OF SUB-MICRON GATE SELF-ALIGNED GaAs FET.

Abstract

Publication series

ASJC Scopus subject areas

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