Energy-efficient dynamic instruction scheduling logic through instruction grouping

Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura

Research output: Contribution to journalArticlepeer-review


Dynamic instruction scheduling logic is quite complex and dissipates significant energy in microprocessors that support superscalar and out-of-order execution. We propose a novel microarchitectural technique to reduce the complexity and energy consumption of the dynamic instruction scheduling logic. The proposed method groups several instructions as a single issue unit and reduces the required number of ports and the size of the structure. This paper describes the microarchitecture mechanisms and shows evaluation results for energy savings and performance. These results reveal that the proposed technique can greatly reduce energy with almost no performance degradation, compared to the conventional dynamic instruction scheduling logic.

Original languageEnglish
Article number4814485
Pages (from-to)848-852
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number6
Publication statusPublished - 2009 Jun
Externally publishedYes


  • Dynamic instruction scheduling
  • Instruction grouping
  • Issue queue

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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