@inproceedings{6d7c2b790b3f402b8a5fe5092f2a81ca,
title = "Enforcing dimension-order routing in on-chip torus networks without virtual channels",
abstract = "In the case of simple tile-based architecture, such as small reconfigurable processor arrays, a virtual-channel mechanism, which requires additional logic and pipeline stages, will be one of the crucial factors for a low cost implementation of their on-chip routers. To guarantee deadlock-free packet transfer with no virtual channels on tori, we propose a non-minimal strategy consistent with the rule of dimension-order routing (DOR) algorithm. Since embedded streaming applications usually generate predictable data traffic, the path set can be customized to the traffic from alternative DOR paths. Although the proposed strategy does not use any virtual channels, it achieves almost the same performance as virtual-channel routers on tori in eleven of 18 application traces.",
author = "Hiroki Matsutani and Michihiro Koibuchi and Hideharu Amano",
note = "Publisher Copyright: {\textcopyright} Springer-Verlag Berlin Heidelberg 2006.; 4th International Symposium on Parallel and Distributed Processing and Applications, ISPA 2006 ; Conference date: 04-12-2006 Through 06-12-2006",
year = "2006",
doi = "10.1007/11946441_23",
language = "English",
isbn = "9783540680673",
series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
publisher = "Springer Verlag",
pages = "207--218",
editor = "Minyi Guo and Yang, {Laurence T} and {Di Martino}, Beniamino and Zima, {Hans P.} and Zima, {Hans P.} and Jack Dongarra and Feilong Tang",
booktitle = "Parallel and Distributed Processing and Applications - 4th International Symposium, ISPA 2006, Proceedings",
}