Fabrication of gate-all-around MOSFET by silicon anisotropic etching technique

Toshikazu Mukaiyama; Ken Ichi Saito; Hiroki Ishikuro; Makoto Takamiya; Takuya Saraya; Toshiro Hiramoto

doi:10.1016/S0038-1101(98)00082-3

Fabrication of gate-all-around MOSFET by silicon anisotropic etching technique

Toshikazu Mukaiyama, Ken Ichi Saito, Hiroki Ishikuro, Makoto Takamiya, Takuya Saraya, Toshiro Hiramoto

Research output: Contribution to journal › Article › peer-review

8 Citations (Scopus)

Abstract

A novel fabrication process of gate-all-around (GAA) MOSFETs using an anisotropic etching technique has been proposed. In this technology, the channel width of the GAA device is not limited by the lithography resolution and the density of the wire channel is doubled. The two-dimensional device simulation shows much better short channel immunity of GAA devices than that of single gate and double gate SOI MOSFETs. The simulation also shows that the new GAA devices we have proposed have higher current drivability than the conventional GAA and single gate SOI devices.

Original language	English
Pages (from-to)	1623-1626
Number of pages	4
Journal	Solid-State Electronics
Volume	42
Issue number	7-8
DOIs	https://doi.org/10.1016/S0038-1101(98)00082-3
Publication status	Published - 1998 Jan 1
Externally published	Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1016/S0038-1101(98)00082-3

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abstract = "A novel fabrication process of gate-all-around (GAA) MOSFETs using an anisotropic etching technique has been proposed. In this technology, the channel width of the GAA device is not limited by the lithography resolution and the density of the wire channel is doubled. The two-dimensional device simulation shows much better short channel immunity of GAA devices than that of single gate and double gate SOI MOSFETs. The simulation also shows that the new GAA devices we have proposed have higher current drivability than the conventional GAA and single gate SOI devices.",

author = "Toshikazu Mukaiyama and Saito, {Ken Ichi} and Hiroki Ishikuro and Makoto Takamiya and Takuya Saraya and Toshiro Hiramoto",

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AU - Mukaiyama, Toshikazu

AU - Saito, Ken Ichi

AU - Ishikuro, Hiroki

AU - Takamiya, Makoto

AU - Saraya, Takuya

AU - Hiramoto, Toshiro

PY - 1998/1/1

Y1 - 1998/1/1

N2 - A novel fabrication process of gate-all-around (GAA) MOSFETs using an anisotropic etching technique has been proposed. In this technology, the channel width of the GAA device is not limited by the lithography resolution and the density of the wire channel is doubled. The two-dimensional device simulation shows much better short channel immunity of GAA devices than that of single gate and double gate SOI MOSFETs. The simulation also shows that the new GAA devices we have proposed have higher current drivability than the conventional GAA and single gate SOI devices.

AB - A novel fabrication process of gate-all-around (GAA) MOSFETs using an anisotropic etching technique has been proposed. In this technology, the channel width of the GAA device is not limited by the lithography resolution and the density of the wire channel is doubled. The two-dimensional device simulation shows much better short channel immunity of GAA devices than that of single gate and double gate SOI MOSFETs. The simulation also shows that the new GAA devices we have proposed have higher current drivability than the conventional GAA and single gate SOI devices.

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JO - Solid-State Electronics

JF - Solid-State Electronics

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ER -

Fabrication of gate-all-around MOSFET by silicon anisotropic etching technique

Abstract

ASJC Scopus subject areas

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