Fine grain partial reconfiguration for energy saving in dynamically reconfigurable processors

Toru Sano; Yoshiki Saito; Masaru Kato; Hideharu Amano

doi:10.1109/FPL.2009.5272435

Fine grain partial reconfiguration for energy saving in dynamically reconfigurable processors

Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Based on the power consumption analysis of a real Dynamically Reconfigurable Processor Array (DRPA) prototype MuCCRA-3, it appears that the key of power saving is keeping the datapath on the Processing Element (PE) array as possible. Fine Grain Partial Reconfiguration (FGPR) is a simple technique to minimize the change of configuration code in a hardware context switching. In FGPR, a configuration code is divided into several components and only the configuration data for the required components are changed. Evaluation results demonstrate that about 15% of the power consumption is reduced with only 0.7% hardware overhead. The total amount of configuration data and its loading time can be also reduced by 37% in average.

Original language	English
Title of host publication	FPL 09
Subtitle of host publication	19th International Conference on Field Programmable Logic and Applications
Pages	530-533
Number of pages	4
DOIs	https://doi.org/10.1109/FPL.2009.5272435
Publication status	Published - 2009 Nov 25
Event	FPL 09: 19th International Conference on Field Programmable Logic and Applications - Prague, Czech Republic Duration: 2009 Aug 31 → 2009 Sept 2

Publication series

Name	FPL 09: 19th International Conference on Field Programmable Logic and Applications

Other

Other	FPL 09: 19th International Conference on Field Programmable Logic and Applications
Country/Territory	Czech Republic
City	Prague
Period	09/8/31 → 09/9/2

ASJC Scopus subject areas

Computational Theory and Mathematics
Computer Science Applications

Access to Document

10.1109/FPL.2009.5272435

Cite this

Sano, T., Saito, Y., Kato, M., & Amano, H. (2009). Fine grain partial reconfiguration for energy saving in dynamically reconfigurable processors. In FPL 09: 19th International Conference on Field Programmable Logic and Applications (pp. 530-533). Article 5272435 (FPL 09: 19th International Conference on Field Programmable Logic and Applications). https://doi.org/10.1109/FPL.2009.5272435

Fine grain partial reconfiguration for energy saving in dynamically reconfigurable processors. / Sano, Toru; Saito, Yoshiki; Kato, Masaru et al.
FPL 09: 19th International Conference on Field Programmable Logic and Applications. 2009. p. 530-533 5272435 (FPL 09: 19th International Conference on Field Programmable Logic and Applications).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sano, T, Saito, Y, Kato, M & Amano, H 2009, Fine grain partial reconfiguration for energy saving in dynamically reconfigurable processors. in FPL 09: 19th International Conference on Field Programmable Logic and Applications., 5272435, FPL 09: 19th International Conference on Field Programmable Logic and Applications, pp. 530-533, FPL 09: 19th International Conference on Field Programmable Logic and Applications, Prague, Czech Republic, 09/8/31. https://doi.org/10.1109/FPL.2009.5272435

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Fine grain partial reconfiguration for energy saving in dynamically reconfigurable processors

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