Folded fat H-Tree: An interconnection topology for dynamically reconfigurable processor array

Yutaka Yamada; Hideharu Amano; Michihiro Koibuchi; Akiya Jouraku; Kenichiro Anjo; Katsunobu Nishimura

doi:10.1007/978-3-540-30121-9_29

Folded fat H-Tree: An interconnection topology for dynamically reconfigurable processor array

Yutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, Katsunobu Nishimura

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Chapter

4 Citations (Scopus)

Abstract

Fat H-Tree is a novel on-chip network topology for a dynamic reconfigurable processor array. It includes both fat tree and torus structure, and suitable to map tasks in a stream processing. For on-chip implementation, folding layout is also proposed. Evaluation results show that Fat H-Tree reduces the distance of H-Tree from 13% to 55%, and stretches the throughput almost three times.

Original language	English
Title of host publication	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Editors	Laurence T. Yang, Minyi Guo, Guang R. Gao, Niraj K. Jha
Publisher	Springer Verlag
Pages	301-311
Number of pages	11
ISBN (Print)	354022906X, 9783540229063
DOIs	https://doi.org/10.1007/978-3-540-30121-9_29
Publication status	Published - 2004

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	3207
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

ASJC Scopus subject areas

Theoretical Computer Science
Computer Science(all)

Access to Document

10.1007/978-3-540-30121-9_29

Cite this

Yamada, Y., Amano, H., Koibuchi, M., Jouraku, A., Anjo, K., & Nishimura, K. (2004). Folded fat H-Tree: An interconnection topology for dynamically reconfigurable processor array. In L. T. Yang, M. Guo, G. R. Gao, & N. K. Jha (Eds.), Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (pp. 301-311). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 3207). Springer Verlag. https://doi.org/10.1007/978-3-540-30121-9_29

Folded fat H-Tree: An interconnection topology for dynamically reconfigurable processor array. / Yamada, Yutaka; Amano, Hideharu; Koibuchi, Michihiro et al.
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). ed. / Laurence T. Yang; Minyi Guo; Guang R. Gao; Niraj K. Jha. Springer Verlag, 2004. p. 301-311 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 3207).

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Yamada, Y, Amano, H, Koibuchi, M, Jouraku, A, Anjo, K & Nishimura, K 2004, Folded fat H-Tree: An interconnection topology for dynamically reconfigurable processor array. in LT Yang, M Guo, GR Gao & NK Jha (eds), Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 3207, Springer Verlag, pp. 301-311. https://doi.org/10.1007/978-3-540-30121-9_29

Yamada Y, Amano H, Koibuchi M, Jouraku A, Anjo K, Nishimura K. Folded fat H-Tree: An interconnection topology for dynamically reconfigurable processor array. In Yang LT, Guo M, Gao GR, Jha NK, editors, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag. 2004. p. 301-311. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-540-30121-9_29

Yamada, Yutaka ; Amano, Hideharu ; Koibuchi, Michihiro et al. / Folded fat H-Tree : An interconnection topology for dynamically reconfigurable processor array. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). editor / Laurence T. Yang ; Minyi Guo ; Guang R. Gao ; Niraj K. Jha. Springer Verlag, 2004. pp. 301-311 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

@inbook{e457cbdd6be94b0fb3efbdf15a4b0968,

title = "Folded fat H-Tree: An interconnection topology for dynamically reconfigurable processor array",

abstract = "Fat H-Tree is a novel on-chip network topology for a dynamic reconfigurable processor array. It includes both fat tree and torus structure, and suitable to map tasks in a stream processing. For on-chip implementation, folding layout is also proposed. Evaluation results show that Fat H-Tree reduces the distance of H-Tree from 13% to 55%, and stretches the throughput almost three times.",

author = "Yutaka Yamada and Hideharu Amano and Michihiro Koibuchi and Akiya Jouraku and Kenichiro Anjo and Katsunobu Nishimura",

year = "2004",

doi = "10.1007/978-3-540-30121-9_29",

language = "English",

isbn = "354022906X",

series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

publisher = "Springer Verlag",

pages = "301--311",

editor = "Yang, {Laurence T.} and Minyi Guo and Gao, {Guang R.} and Jha, {Niraj K.}",

booktitle = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

}

TY - CHAP

T1 - Folded fat H-Tree

T2 - An interconnection topology for dynamically reconfigurable processor array

AU - Yamada, Yutaka

AU - Amano, Hideharu

AU - Koibuchi, Michihiro

AU - Jouraku, Akiya

AU - Anjo, Kenichiro

AU - Nishimura, Katsunobu

PY - 2004

Y1 - 2004

N2 - Fat H-Tree is a novel on-chip network topology for a dynamic reconfigurable processor array. It includes both fat tree and torus structure, and suitable to map tasks in a stream processing. For on-chip implementation, folding layout is also proposed. Evaluation results show that Fat H-Tree reduces the distance of H-Tree from 13% to 55%, and stretches the throughput almost three times.

AB - Fat H-Tree is a novel on-chip network topology for a dynamic reconfigurable processor array. It includes both fat tree and torus structure, and suitable to map tasks in a stream processing. For on-chip implementation, folding layout is also proposed. Evaluation results show that Fat H-Tree reduces the distance of H-Tree from 13% to 55%, and stretches the throughput almost three times.

UR - http://www.scopus.com/inward/record.url?scp=35048885612&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=35048885612&partnerID=8YFLogxK

U2 - 10.1007/978-3-540-30121-9_29

DO - 10.1007/978-3-540-30121-9_29

M3 - Chapter

AN - SCOPUS:35048885612

SN - 354022906X

SN - 9783540229063

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 301

EP - 311

BT - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

A2 - Yang, Laurence T.

A2 - Guo, Minyi

A2 - Gao, Guang R.

A2 - Jha, Niraj K.

PB - Springer Verlag

ER -

Folded fat H-Tree: An interconnection topology for dynamically reconfigurable processor array

Abstract

Publication series

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this