FPL Demo: An FPGA-IP Prototype Chip for MEC devices

Morihiro Kuga; Masahiro Iida; Hideharu Amano

doi:10.1109/FPL57034.2022.00083

FPL Demo: An FPGA-IP Prototype Chip for MEC devices

Morihiro Kuga, Masahiro Iida, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This demonstration shows a prototype chip of SLM (Scalable Logic Module) for a novel FPGA-IP embedded in various chips for edge computing. In this paper, the authors briefly describe the architecture of our FPGA-IP and the evaluation environment for the prototype chip.

Original language	English
Title of host publication	Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	467
Number of pages	1
ISBN (Electronic)	9781665473903
DOIs	https://doi.org/10.1109/FPL57034.2022.00083
Publication status	Published - 2022
Event	32nd International Conference on Field-Programmable Logic and Applications, FPL 2022 - Belfast, United Kingdom Duration: 2022 Aug 29 → 2022 Sept 2

Publication series

Name	Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022

Conference

Conference	32nd International Conference on Field-Programmable Logic and Applications, FPL 2022
Country/Territory	United Kingdom
City	Belfast
Period	22/8/29 → 22/9/2

Keywords

FPGA
IoT
Multi-access Edge Computing

ASJC Scopus subject areas

Artificial Intelligence
Computer Science Applications
Software
Control and Optimization
Instrumentation
Hardware and Architecture

Access to Document

10.1109/FPL57034.2022.00083

Cite this

Kuga, M., Iida, M., & Amano, H. (2022). FPL Demo: An FPGA-IP Prototype Chip for MEC devices. In Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022 (pp. 467). (Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPL57034.2022.00083

FPL Demo: An FPGA-IP Prototype Chip for MEC devices. / Kuga, Morihiro; Iida, Masahiro; Amano, Hideharu.
Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 467 (Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kuga, M, Iida, M & Amano, H 2022, FPL Demo: An FPGA-IP Prototype Chip for MEC devices. in Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022. Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022, Institute of Electrical and Electronics Engineers Inc., pp. 467, 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022, Belfast, United Kingdom, 22/8/29. https://doi.org/10.1109/FPL57034.2022.00083

Kuga M, Iida M, Amano H. FPL Demo: An FPGA-IP Prototype Chip for MEC devices. In Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 467. (Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022). doi: 10.1109/FPL57034.2022.00083

Kuga, Morihiro ; Iida, Masahiro ; Amano, Hideharu. / FPL Demo : An FPGA-IP Prototype Chip for MEC devices. Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022. Institute of Electrical and Electronics Engineers Inc., 2022. pp. 467 (Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022).

@inproceedings{4645b1931d2c4a7890d597111790a3c6,

title = "FPL Demo: An FPGA-IP Prototype Chip for MEC devices",

abstract = "This demonstration shows a prototype chip of SLM (Scalable Logic Module) for a novel FPGA-IP embedded in various chips for edge computing. In this paper, the authors briefly describe the architecture of our FPGA-IP and the evaluation environment for the prototype chip.",

keywords = "FPGA, IoT, Multi-access Edge Computing",

author = "Morihiro Kuga and Masahiro Iida and Hideharu Amano",

note = "Funding Information: IV. DEMONSTRATION We will demonstrate the real prototype chip working for several applications, and its design tools. This work was supported by JST CREST Grant Number JPMJCR19K1. Publisher Copyright: {\textcopyright} 2022 IEEE.; 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022 ; Conference date: 29-08-2022 Through 02-09-2022",

year = "2022",

doi = "10.1109/FPL57034.2022.00083",

language = "English",

series = "Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "467",

booktitle = "Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022",

}

TY - GEN

T1 - FPL Demo

T2 - 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022

AU - Kuga, Morihiro

AU - Iida, Masahiro

AU - Amano, Hideharu

N1 - Funding Information: IV. DEMONSTRATION We will demonstrate the real prototype chip working for several applications, and its design tools. This work was supported by JST CREST Grant Number JPMJCR19K1. Publisher Copyright: © 2022 IEEE.

PY - 2022

Y1 - 2022

N2 - This demonstration shows a prototype chip of SLM (Scalable Logic Module) for a novel FPGA-IP embedded in various chips for edge computing. In this paper, the authors briefly describe the architecture of our FPGA-IP and the evaluation environment for the prototype chip.

AB - This demonstration shows a prototype chip of SLM (Scalable Logic Module) for a novel FPGA-IP embedded in various chips for edge computing. In this paper, the authors briefly describe the architecture of our FPGA-IP and the evaluation environment for the prototype chip.

KW - FPGA

KW - IoT

KW - Multi-access Edge Computing

UR - http://www.scopus.com/inward/record.url?scp=85149288855&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85149288855&partnerID=8YFLogxK

U2 - 10.1109/FPL57034.2022.00083

DO - 10.1109/FPL57034.2022.00083

M3 - Conference contribution

AN - SCOPUS:85149288855

T3 - Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022

SP - 467

BT - Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 29 August 2022 through 2 September 2022

ER -

FPL Demo: An FPGA-IP Prototype Chip for MEC devices

Abstract

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Keywords

ASJC Scopus subject areas

Access to Document

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