Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA

  • Hiroshi Nakano
  • , Krzysztof Blachut
  • , Kamil Jeziorek
  • , Piotr Wzorek
  • , Manon Dampfhoffer
  • , Thomas Mesquida
  • , Hiroaki Nishi
  • , Tomasz Kryjak
  • , Thomas Dalgaty

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Computer Science

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