Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation

Katsuki Ohata; Yuki Sanada; Tetsuro Ogaki; Kento Matsuyama; Takanori Ohira; Satoshi Chikuda; Masaki Igarashi; Masayuki Ikebe; Tetsuya Asai; Masato Motomura; Tadahiro Kuroda

doi:10.1109/ICECS.2013.6815381

Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation

Katsuki Ohata, Yuki Sanada, Tetsuro Ogaki, Kento Matsuyama, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

This paper presents a novel hardware-oriented stereo vision system based on 1-D cost aggregation. Many researchers have implemented hardware efficient stereo matching to realize real-time systems. However, such methods require a large amount of memory. We proposed a system that is based on a hardware-software hybrid architecture for memory reduction. It consisted of grayscale 1-D cost aggregation HW and 2-D disparity refinement SW. The 1-D processing reduced the size of RAM in our HW to 266 kb with an input image size of 1024×768. We achieved the average error rate for the Middlebury datasets as 6.24%. The processing time was 56.6 ms for the 1024×768 images and an average of 8.6 ms for the Middlebury datasets which have an average size of 400×380. Using the resolution of Middlebury datasets, our system can perform real-time depth-aided image processing.

Original language	English
Title of host publication	2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	169-172
Number of pages	4
ISBN (Print)	9781479924523
DOIs	https://doi.org/10.1109/ICECS.2013.6815381
Publication status	Published - 2013
Externally published	Yes
Event	2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013 - Abu Dhabi, United Arab Emirates Duration: 2013 Dec 8 → 2013 Dec 11

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Other

Other	2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013
Country/Territory	United Arab Emirates
City	Abu Dhabi
Period	13/12/8 → 13/12/11

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ICECS.2013.6815381

Cite this

Ohata, K., Sanada, Y., Ogaki, T., Matsuyama, K., Ohira, T., Chikuda, S., Igarashi, M., Ikebe, M., Asai, T., Motomura, M., & Kuroda, T. (2013). Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation. In 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013 (pp. 169-172). Article 6815381 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.2013.6815381

Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation. / Ohata, Katsuki; Sanada, Yuki; Ogaki, Tetsuro et al.
2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013. Institute of Electrical and Electronics Engineers Inc., 2013. p. 169-172 6815381 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ohata, K, Sanada, Y, Ogaki, T, Matsuyama, K, Ohira, T, Chikuda, S, Igarashi, M, Ikebe, M, Asai, T, Motomura, M & Kuroda, T 2013, Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation. in 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013., 6815381, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, Institute of Electrical and Electronics Engineers Inc., pp. 169-172, 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013, Abu Dhabi, United Arab Emirates, 13/12/8. https://doi.org/10.1109/ICECS.2013.6815381

Ohata K, Sanada Y, Ogaki T, Matsuyama K, Ohira T, Chikuda S et al. Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation. In 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013. Institute of Electrical and Electronics Engineers Inc. 2013. p. 169-172. 6815381. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). doi: 10.1109/ICECS.2013.6815381

Ohata, Katsuki ; Sanada, Yuki ; Ogaki, Tetsuro et al. / Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation. 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013. Institute of Electrical and Electronics Engineers Inc., 2013. pp. 169-172 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

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abstract = "This paper presents a novel hardware-oriented stereo vision system based on 1-D cost aggregation. Many researchers have implemented hardware efficient stereo matching to realize real-time systems. However, such methods require a large amount of memory. We proposed a system that is based on a hardware-software hybrid architecture for memory reduction. It consisted of grayscale 1-D cost aggregation HW and 2-D disparity refinement SW. The 1-D processing reduced the size of RAM in our HW to 266 kb with an input image size of 1024×768. We achieved the average error rate for the Middlebury datasets as 6.24%. The processing time was 56.6 ms for the 1024×768 images and an average of 8.6 ms for the Middlebury datasets which have an average size of 400×380. Using the resolution of Middlebury datasets, our system can perform real-time depth-aided image processing.",

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AU - Chikuda, Satoshi

AU - Igarashi, Masaki

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Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation

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