High-speed ATM switch with input and cross-point buffers

Yukihiro Doi, Naoaki Yamanaka

Research output: Contribution to journalArticlepeer-review

31 Citations (Scopus)


This letter describes a new input and cross-point buffering matrix switching architecture for high-speed ATM switching systems. The proposed switch has input queuing buffers at each input port, and small size buffers for output port arbitration at each cross-point. These two types of buffers share loads using a simple and high-speed retry algorithm. Hardware size is only half that of conventional cross-point buffering switches. In addition, the switch achieves high-throughput at a condition that the switching speed matches the input and output port speed. This switch is expected to enable the development of high-speed ATM switching systems with each port supporting speeds in excess of 1 Gbit/s.

Original languageEnglish
Pages (from-to)310-314
Number of pages5
JournalIEICE Transactions on Communications
Issue number3
Publication statusPublished - 1993 Mar 1
Externally publishedYes

ASJC Scopus subject areas

  • Software
  • Computer Networks and Communications
  • Electrical and Electronic Engineering


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