High-speed decompression architecture of compressed HTTP streams for the internet routers

Hironori Okano; Hayato Yamaki; Hiroaki Nishi

doi:10.1109/FPGA4GPC.2016.7518531

High-speed decompression architecture of compressed HTTP streams for the internet routers

Hironori Okano, Hayato Yamaki, Hiroaki Nishi

Department of System Design Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

In recent years, studies of DPI have been carried out actively. HTTP packets, which are a kind of DPI target, include GZIP compressed packets, and multi-streamed GZIP compressed HTTP cannot be analyzed directly on routers. Moreover, wire-rate processing is required to achieve on-router analysis. In this paper, HTTP decompressing architecture on routers supporting 40Gbps network is considered, and three mechanisms, which are parallelized architecture, cache architecture and piggy-back method, were proposed for achieving higher throughput. Hardware cost simulations by using Verilog HDL confirms it can achieve 10Gbps throughput at low circuit costs.

Original language	English
Title of host publication	2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016
Editors	Jan Haase, Dominik Meyer
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	31-36
Number of pages	6
ISBN (Electronic)	9781509013593
DOIs	https://doi.org/10.1109/FPGA4GPC.2016.7518531
Publication status	Published - 2016 Jul 20
Event	2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016 - Hamburg, Germany Duration: 2016 May 9 → 2016 May 10

Publication series

Name	2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016

Other

Other	2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016
Country/Territory	Germany
City	Hamburg
Period	16/5/9 → 16/5/10

Keywords

GZIP Decompression
HTTP compression
Network Router
Parallel Processing

ASJC Scopus subject areas

Hardware and Architecture

Access to Document

10.1109/FPGA4GPC.2016.7518531

Cite this

Okano, H., Yamaki, H., & Nishi, H. (2016). High-speed decompression architecture of compressed HTTP streams for the internet routers. In J. Haase, & D. Meyer (Eds.), 2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016 (pp. 31-36). Article 7518531 (2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPGA4GPC.2016.7518531

High-speed decompression architecture of compressed HTTP streams for the internet routers. / Okano, Hironori; Yamaki, Hayato; Nishi, Hiroaki.
2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016. ed. / Jan Haase; Dominik Meyer. Institute of Electrical and Electronics Engineers Inc., 2016. p. 31-36 7518531 (2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Okano, H, Yamaki, H & Nishi, H 2016, High-speed decompression architecture of compressed HTTP streams for the internet routers. in J Haase & D Meyer (eds), 2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016., 7518531, 2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016, Institute of Electrical and Electronics Engineers Inc., pp. 31-36, 2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016, Hamburg, Germany, 16/5/9. https://doi.org/10.1109/FPGA4GPC.2016.7518531

Okano H, Yamaki H, Nishi H. High-speed decompression architecture of compressed HTTP streams for the internet routers. In Haase J, Meyer D, editors, 2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 31-36. 7518531. (2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016). doi: 10.1109/FPGA4GPC.2016.7518531

Okano, Hironori ; Yamaki, Hayato ; Nishi, Hiroaki. / High-speed decompression architecture of compressed HTTP streams for the internet routers. 2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016. editor / Jan Haase ; Dominik Meyer. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 31-36 (2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016).

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abstract = "In recent years, studies of DPI have been carried out actively. HTTP packets, which are a kind of DPI target, include GZIP compressed packets, and multi-streamed GZIP compressed HTTP cannot be analyzed directly on routers. Moreover, wire-rate processing is required to achieve on-router analysis. In this paper, HTTP decompressing architecture on routers supporting 40Gbps network is considered, and three mechanisms, which are parallelized architecture, cache architecture and piggy-back method, were proposed for achieving higher throughput. Hardware cost simulations by using Verilog HDL confirms it can achieve 10Gbps throughput at low circuit costs.",

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High-speed decompression architecture of compressed HTTP streams for the internet routers

Abstract

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Keywords

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