High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme

Tadahiro Kuroda; Tetsuya Fujita; Tetsu Nagamatu; Shinichi Yoshioka; Toshikazu Sei; Kenji Matsuo; Yoichiro Hamura; Toshiaki Mori; Masayuki Murota; Masakazu Kakumu; Takayasu Sakurai

High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme

Tadahiro Kuroda, Tetsuya Fujita, Tetsu Nagamatu, Shinichi Yoshioka, Toshikazu Sei, Kenji Matsuo, Yoichiro Hamura, Toshiaki Mori, Masayuki Murota, Masakazu Kakumu, Takayasu Sakurai

Research output: Contribution to journal › Conference article › peer-review

36 Citations (Scopus)

Abstract

Circuit techniques for dynamically varying threshold voltage are introduced to reduce active power dissipation by 50% with negligible overhead in speed, standby power and chip area. No additional external power supply or additional step in process is required. A gate array with this scheme is fabricated in a 0.3μm CMOS technology whose performance is investigated. The gate array is best fit for multimedia portable applications that require low standby power dissipation and high performance.

Original language	English
Pages (from-to)	53-56
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
Publication status	Published - 1996 Jan 1
Externally published	Yes
Event	Proceedings of the 1996 IEEE Custom Integrated Circuits Conference - San Diego, CA, USA Duration: 1996 May 5 → 1996 May 8

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

@article{551125c131b64e7e902b6e6b94ce54e3,

title = "High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme",

abstract = "Circuit techniques for dynamically varying threshold voltage are introduced to reduce active power dissipation by 50% with negligible overhead in speed, standby power and chip area. No additional external power supply or additional step in process is required. A gate array with this scheme is fabricated in a 0.3μm CMOS technology whose performance is investigated. The gate array is best fit for multimedia portable applications that require low standby power dissipation and high performance.",

author = "Tadahiro Kuroda and Tetsuya Fujita and Tetsu Nagamatu and Shinichi Yoshioka and Toshikazu Sei and Kenji Matsuo and Yoichiro Hamura and Toshiaki Mori and Masayuki Murota and Masakazu Kakumu and Takayasu Sakurai",

year = "1996",

month = jan,

day = "1",

language = "English",

pages = "53--56",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1996 IEEE Custom Integrated Circuits Conference ; Conference date: 05-05-1996 Through 08-05-1996",

}

TY - JOUR

T1 - High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme

AU - Kuroda, Tadahiro

AU - Fujita, Tetsuya

AU - Nagamatu, Tetsu

AU - Yoshioka, Shinichi

AU - Sei, Toshikazu

AU - Matsuo, Kenji

AU - Hamura, Yoichiro

AU - Mori, Toshiaki

AU - Murota, Masayuki

AU - Kakumu, Masakazu

AU - Sakurai, Takayasu

PY - 1996/1/1

Y1 - 1996/1/1

N2 - Circuit techniques for dynamically varying threshold voltage are introduced to reduce active power dissipation by 50% with negligible overhead in speed, standby power and chip area. No additional external power supply or additional step in process is required. A gate array with this scheme is fabricated in a 0.3μm CMOS technology whose performance is investigated. The gate array is best fit for multimedia portable applications that require low standby power dissipation and high performance.

AB - Circuit techniques for dynamically varying threshold voltage are introduced to reduce active power dissipation by 50% with negligible overhead in speed, standby power and chip area. No additional external power supply or additional step in process is required. A gate array with this scheme is fabricated in a 0.3μm CMOS technology whose performance is investigated. The gate array is best fit for multimedia portable applications that require low standby power dissipation and high performance.

UR - http://www.scopus.com/inward/record.url?scp=0029700814&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029700814&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0029700814

SN - 0886-5930

SP - 53

EP - 56

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

T2 - Proceedings of the 1996 IEEE Custom Integrated Circuits Conference

Y2 - 5 May 1996 through 8 May 1996

ER -

High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme

Abstract

ASJC Scopus subject areas

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