IMPLEMENTATION OF A NEW TYPE DSP PLL USING HIGH PERFORMANCE DSP DSSP-1.

S. Ono; T. Aoyama; M. Hagiwara; M. Nakagawa

IMPLEMENTATION OF A NEW TYPE DSP PLL USING HIGH PERFORMANCE DSP DSSP-1.

S. Ono, T. Aoyama, M. Hagiwara, M. Nakagawa

Research output: Contribution to journal › Conference article › peer-review

Abstract

The authors describe a new digital processing phase lock loop (PLL) implemented on the DSSP 1 high-performance digital signal processor. The new PLL has linear phase comparison characteristics and is called the linear digital PLL. It exhibits fast acquisition without an increase in jitter, its pull-in range is wider, and its steady-state errors and sampling frequency are lower than those of conventional PLLs. It also does not require automatic gain control.

Original language	English
Pages (from-to)	2195-2198
Number of pages	4
Journal	ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Publication status	Published - 1986 Dec 1
Externally published	Yes

ASJC Scopus subject areas

Software
Signal Processing
Electrical and Electronic Engineering

Cite this

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title = "IMPLEMENTATION OF A NEW TYPE DSP PLL USING HIGH PERFORMANCE DSP DSSP-1.",

abstract = "The authors describe a new digital processing phase lock loop (PLL) implemented on the DSSP 1 high-performance digital signal processor. The new PLL has linear phase comparison characteristics and is called the linear digital PLL. It exhibits fast acquisition without an increase in jitter, its pull-in range is wider, and its steady-state errors and sampling frequency are lower than those of conventional PLLs. It also does not require automatic gain control.",

author = "S. Ono and T. Aoyama and M. Hagiwara and M. Nakagawa",

year = "1986",

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AU - Ono, S.

AU - Aoyama, T.

AU - Hagiwara, M.

AU - Nakagawa, M.

PY - 1986/12/1

Y1 - 1986/12/1

N2 - The authors describe a new digital processing phase lock loop (PLL) implemented on the DSSP 1 high-performance digital signal processor. The new PLL has linear phase comparison characteristics and is called the linear digital PLL. It exhibits fast acquisition without an increase in jitter, its pull-in range is wider, and its steady-state errors and sampling frequency are lower than those of conventional PLLs. It also does not require automatic gain control.

AB - The authors describe a new digital processing phase lock loop (PLL) implemented on the DSSP 1 high-performance digital signal processor. The new PLL has linear phase comparison characteristics and is called the linear digital PLL. It exhibits fast acquisition without an increase in jitter, its pull-in range is wider, and its steady-state errors and sampling frequency are lower than those of conventional PLLs. It also does not require automatic gain control.

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JO - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

JF - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

ER -

IMPLEMENTATION OF A NEW TYPE DSP PLL USING HIGH PERFORMANCE DSP DSSP-1.

Abstract

ASJC Scopus subject areas

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