Abstract
In order to manipulate SHD (super high definition) images, a novel parallel processing unit called HiPIPE (Highly Parallel Image Processing Engine) is developed as a project of NOVI-II. The engine is connected to an SHD image display unit and an image data storage unit. Extremely high computational power is obtained by a multicomputer type parallel processing technique. 128 processing elements are connected by a mesh network. Various image coding schemes are carefully explored from the viewpoint of parallel processing, and the problem of processor connections is examined. A novel load-balancing technique, called 2-dimensional butterfly data shuffling, is developed and implemented. The current version of HiPIPE uses just 128 scaler processing elements and has more than twice the power of a single-processor CRAY-2 for a still SHD image coding task.
| Original language | English |
|---|---|
| Pages (from-to) | 348-351 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 1 |
| Publication status | Published - 1991 Dec 1 |
| Event | 1991 IEEE International Symposium on Circuits and Systems Part 1 (of 5) - Singapore, Singapore Duration: 1991 Jun 11 → 1991 Jun 14 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering