I/Q mismatch compensation ΔΣ modulator using ternary capacitor rotation technique

Masaki Yonekura, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a new technique to suppress I/Q mismatch and decrease power consumption and chip area. The proposed technique uses two methods for all integrators and DAC in the modulator which are main sources of the mismatch and power. One is proposed ternary capacitor rotation technique to compensate the I/Q mismatch and achieve high image-rejection. The other is amplifier-sharing technique to reduce the number of amplifier and power consumption. The third-order 1bit delta-sigma modulator was designed in 65nm CMOS process, and fabricated test chip achieved an image-rejection ratio (IRR) of higher than 70dB throughout a 1MHz bandwidth. The overall power consumption is 12.7mW including I/Q channels.

Original languageEnglish
Title of host publicationESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference
EditorsFranz Dielacher, Wolfgang Pribyl, Gernot Hueber
PublisherIEEE Computer Society
Pages229-232
Number of pages4
ISBN (Electronic)9781467374705
DOIs
Publication statusPublished - 2015 Oct 30
Event41st European Solid-State Circuits Conference, ESSCIRC 2015 - Graz, Austria
Duration: 2015 Sept 142015 Sept 18

Publication series

NameEuropean Solid-State Circuits Conference
Volume2015-October
ISSN (Print)1930-8833

Other

Other41st European Solid-State Circuits Conference, ESSCIRC 2015
Country/TerritoryAustria
CityGraz
Period15/9/1415/9/18

Keywords

  • I/Q mismatch
  • amplifier-sharing
  • delta-sigma modulator
  • image-rejection

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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