Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique

Yoshiki Saito; Tomoaki Shirai; Takuro Nakamura; Takashi Nishimura; Yohei Hasegawa; Satoshi Tsutsumi; Toshihiro Kashima; Mitsutaka Nakata; Seidai Takeda; Kimiyoshi Usami; Hideharu Amano

doi:10.1109/FPT.2008.4762410

Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique

Yoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

15 Citations (Scopus)

Abstract

One of the benefits of coarse grained dynamically re-configurable processor array(DRPA) is its low dynamic power consumption by operating a number of processing elements(PE) in parallel with low clock frequency. However, in the future advanced processes, leakage power will occupy a considerable part of the total power consumption, and it may degrade the advantage of DRPAs. In order to reduce the leakage power, a fine grained Power Gating(PG) is applied to a DRPA, MuCCRA-2.32b, and leakage power and area overhead are measured. We evaluated the effect of two control modes; Pair and Unit Individual based on layout design and real applications. It appears that by applying PG for ALUs and SMUs in PEs individually, 48% of leakage power can be reduced with 9.0% of area overhead.

Original language	English
Title of host publication	Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008
Pages	329-332
Number of pages	4
DOIs	https://doi.org/10.1109/FPT.2008.4762410
Publication status	Published - 2008
Event	2008 International Conference on Field-Programmable Technology, ICFPT 2008 - Taipei, Taiwan, Province of China Duration: 2008 Dec 7 → 2008 Dec 10

Publication series

Name	Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008

Other

Other	2008 International Conference on Field-Programmable Technology, ICFPT 2008
Country/Territory	Taiwan, Province of China
City	Taipei
Period	08/12/7 → 08/12/10

ASJC Scopus subject areas

Computer Science Applications
Hardware and Architecture

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10.1109/FPT.2008.4762410

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Saito, Y., Shirai, T., Nakamura, T., Nishimura, T., Hasegawa, Y., Tsutsumi, S., Kashima, T., Nakata, M., Takeda, S., Usami, K., & Amano, H. (2008). Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique. In Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008 (pp. 329-332). Article 4762410 (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008). https://doi.org/10.1109/FPT.2008.4762410

Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique. / Saito, Yoshiki; Shirai, Tomoaki; Nakamura, Takuro et al.
Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. 2008. p. 329-332 4762410 (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Saito, Y, Shirai, T, Nakamura, T, Nishimura, T, Hasegawa, Y, Tsutsumi, S, Kashima, T, Nakata, M, Takeda, S, Usami, K & Amano, H 2008, Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique. in Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008., 4762410, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008, pp. 329-332, 2008 International Conference on Field-Programmable Technology, ICFPT 2008, Taipei, Taiwan, Province of China, 08/12/7. https://doi.org/10.1109/FPT.2008.4762410

Saito Y, Shirai T, Nakamura T, Nishimura T, Hasegawa Y, Tsutsumi S et al. Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique. In Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. 2008. p. 329-332. 4762410. (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008). doi: 10.1109/FPT.2008.4762410

Saito, Yoshiki ; Shirai, Tomoaki ; Nakamura, Takuro et al. / Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique. Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. 2008. pp. 329-332 (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008).

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AU - Hasegawa, Yohei

AU - Tsutsumi, Satoshi

AU - Kashima, Toshihiro

AU - Nakata, Mitsutaka

AU - Takeda, Seidai

AU - Usami, Kimiyoshi

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AB - One of the benefits of coarse grained dynamically re-configurable processor array(DRPA) is its low dynamic power consumption by operating a number of processing elements(PE) in parallel with low clock frequency. However, in the future advanced processes, leakage power will occupy a considerable part of the total power consumption, and it may degrade the advantage of DRPAs. In order to reduce the leakage power, a fine grained Power Gating(PG) is applied to a DRPA, MuCCRA-2.32b, and leakage power and area overhead are measured. We evaluated the effect of two control modes; Pair and Unit Individual based on layout design and real applications. It appears that by applying PG for ALUs and SMUs in PEs individually, 48% of leakage power can be reduced with 9.0% of area overhead.

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Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique

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