Low power CMOS design challenges

T. Kuroda

    Research output: Contribution to journalArticlepeer-review

    7 Citations (Scopus)


    Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.

    Original languageEnglish
    Pages (from-to)1021-1028
    Number of pages8
    JournalIEICE Transactions on Electronics
    Issue number8
    Publication statusPublished - 2001 Aug


    • Downsizing
    • Low power CMOS design
    • Low voltage
    • Subthreshold leakage current
    • Threshold voltage

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering


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