Abstract
This paper presents the development of high-speed logic ICs having the same function as the ECL100K family for high-speed digital system applications such as for time division switching systems. A Super-Self-Aligned process Technology (SST) and a low-voltage swing differential circuit technique are used. The ICs operate up to about 2 Gb/s under a chip power dissipation of 170 mw-570 mw.
Original language | English |
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Pages (from-to) | 1068-1071 |
Number of pages | 4 |
Journal | Transactions of the Institute of Electronics and Communication Engineers of Japan. Section E |
Volume | E69 |
Issue number | 10 |
Publication status | Published - 1986 Oct 1 |
Externally published | Yes |
ASJC Scopus subject areas
- Engineering(all)