TY - GEN
T1 - Multi-Layer In-Memory Processing
AU - Fujiki, Daichi
AU - Khadem, Alireza
AU - Mahlke, Scott
AU - Das, Reetuparna
N1 - Funding Information:
ACKNOWLEDGMENT We thank the anonymous reviewers for their suggestions which helped improve this paper. This work was supported in part by the NSF under the CAREER-1652294 and NSF-1908601 awards, JSPS KAKENHI Grant Number JP22K21284, and the Applications Driving Architectures (ADA) Research Center, a JUMP Center co-sponsored by SRC and DARPA.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - In-memory computing provides revolutionary changes to computer architecture by fusing memory and computation, allowing data-intensive computations to reduce data communications. Despite promising results of in-memory computing in each layer of the memory hierarchy, an integrated approach to a system with multiple computable memories has not been examined. This paper presents a holistic and application-driven approach to building Multi-Layer In-Memory Processing (MLIMP) systems, enabling applications with variable computation demands to reap the benefits of heterogeneous compute resources in an integrated MLIMP system. By introducing concurrent task scheduling to MLIMP, we achieve improved performance and energy efficiency for graph neural networks and multiprogramming of data parallel applications.
AB - In-memory computing provides revolutionary changes to computer architecture by fusing memory and computation, allowing data-intensive computations to reduce data communications. Despite promising results of in-memory computing in each layer of the memory hierarchy, an integrated approach to a system with multiple computable memories has not been examined. This paper presents a holistic and application-driven approach to building Multi-Layer In-Memory Processing (MLIMP) systems, enabling applications with variable computation demands to reap the benefits of heterogeneous compute resources in an integrated MLIMP system. By introducing concurrent task scheduling to MLIMP, we achieve improved performance and energy efficiency for graph neural networks and multiprogramming of data parallel applications.
KW - accelerator
KW - GNN
KW - in-memory computing
KW - processing in memory
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U2 - 10.1109/MICRO56248.2022.00068
DO - 10.1109/MICRO56248.2022.00068
M3 - Conference contribution
AN - SCOPUS:85141667007
T3 - Proceedings of the Annual International Symposium on Microarchitecture, MICRO
SP - 920
EP - 936
BT - Proceedings - 2022 55th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2022
PB - IEEE Computer Society
T2 - 55th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2022
Y2 - 1 October 2022 through 5 October 2022
ER -
