Namacha: A software development environment for a multi-chip convolutional network accelerator

Tetsui Ohkubo; Ryo Takata; Ryuichi Sakamoto; Masaaki Kondo; Hideharu Amano

Namacha: A software development environment for a multi-chip convolutional network accelerator

Tetsui Ohkubo, Ryo Takata, Ryuichi Sakamoto, Masaaki Kondo, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

A building block convolutional neural network accelerator consists of a host and multiple accelerator chips which can scale the performance by changing the number of stacked chips. In order to program the host and the accelerators, an integrated programming development environment called NAMACHA is proposed. It includes compilers for convolutional neural network accelerators and a system level simulator including inter-chip communication latency. On the simulator, the total application runs 4390x faster than that of the logic level simulation with 1.27% difference of clock cycle counts.

Original language	English
Title of host publication	Proceedings of the 32nd International Conference on Computers and Their Applications, CATA 2017
Publisher	The International Society for Computers and Their Applications (ISCA)
Pages	101-106
Number of pages	6
ISBN (Electronic)	9781943436064
Publication status	Published - 2017
Event	32nd International Conference on Computers and Their Applications, CATA 2017 - Honolulu, United States Duration: 2017 Mar 20 → 2017 Mar 22

Other

Other	32nd International Conference on Computers and Their Applications, CATA 2017
Country/Territory	United States
City	Honolulu
Period	17/3/20 → 17/3/22

ASJC Scopus subject areas

Computer Science Applications

Cite this

Namacha: A software development environment for a multi-chip convolutional network accelerator. / Ohkubo, Tetsui; Takata, Ryo; Sakamoto, Ryuichi et al.
Proceedings of the 32nd International Conference on Computers and Their Applications, CATA 2017. The International Society for Computers and Their Applications (ISCA), 2017. p. 101-106.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ohkubo, T, Takata, R, Sakamoto, R, Kondo, M & Amano, H 2017, Namacha: A software development environment for a multi-chip convolutional network accelerator. in Proceedings of the 32nd International Conference on Computers and Their Applications, CATA 2017. The International Society for Computers and Their Applications (ISCA), pp. 101-106, 32nd International Conference on Computers and Their Applications, CATA 2017, Honolulu, United States, 17/3/20.

@inproceedings{1bc7a806924f4383894ca63844710a7d,

title = "Namacha: A software development environment for a multi-chip convolutional network accelerator",

abstract = "A building block convolutional neural network accelerator consists of a host and multiple accelerator chips which can scale the performance by changing the number of stacked chips. In order to program the host and the accelerators, an integrated programming development environment called NAMACHA is proposed. It includes compilers for convolutional neural network accelerators and a system level simulator including inter-chip communication latency. On the simulator, the total application runs 4390x faster than that of the logic level simulation with 1.27% difference of clock cycle counts.",

author = "Tetsui Ohkubo and Ryo Takata and Ryuichi Sakamoto and Masaaki Kondo and Hideharu Amano",

year = "2017",

language = "English",

pages = "101--106",

booktitle = "Proceedings of the 32nd International Conference on Computers and Their Applications, CATA 2017",

publisher = "The International Society for Computers and Their Applications (ISCA)",

note = "32nd International Conference on Computers and Their Applications, CATA 2017 ; Conference date: 20-03-2017 Through 22-03-2017",

}

TY - GEN

T1 - Namacha

T2 - 32nd International Conference on Computers and Their Applications, CATA 2017

AU - Ohkubo, Tetsui

AU - Takata, Ryo

AU - Sakamoto, Ryuichi

AU - Kondo, Masaaki

AU - Amano, Hideharu

PY - 2017

Y1 - 2017

N2 - A building block convolutional neural network accelerator consists of a host and multiple accelerator chips which can scale the performance by changing the number of stacked chips. In order to program the host and the accelerators, an integrated programming development environment called NAMACHA is proposed. It includes compilers for convolutional neural network accelerators and a system level simulator including inter-chip communication latency. On the simulator, the total application runs 4390x faster than that of the logic level simulation with 1.27% difference of clock cycle counts.

AB - A building block convolutional neural network accelerator consists of a host and multiple accelerator chips which can scale the performance by changing the number of stacked chips. In order to program the host and the accelerators, an integrated programming development environment called NAMACHA is proposed. It includes compilers for convolutional neural network accelerators and a system level simulator including inter-chip communication latency. On the simulator, the total application runs 4390x faster than that of the logic level simulation with 1.27% difference of clock cycle counts.

UR - http://www.scopus.com/inward/record.url?scp=85016611597&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85016611597&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:85016611597

SP - 101

EP - 106

BT - Proceedings of the 32nd International Conference on Computers and Their Applications, CATA 2017

PB - The International Society for Computers and Their Applications (ISCA)

Y2 - 20 March 2017 through 22 March 2017

ER -

Namacha: A software development environment for a multi-chip convolutional network accelerator

Abstract

Other

ASJC Scopus subject areas

Other files and links

Fingerprint

Cite this