TY - JOUR
T1 - Novel chip stacking methods to extend both horizontally and vertically for many-core architectures with ThrouChip interface
AU - Nakahara, Hiroshi
AU - Ozaki, Tomoya
AU - Matsutani, Hiroki
AU - Koibuchi, Michihiro
AU - Amano, Hideharu
N1 - Funding Information:
This work was partially supported by JSPS KAKENHI S Grant Number 25220002.
Publisher Copyright:
© Copyright 2016 The Institute of Electronics, Information and Communication Engineers.
PY - 2016/12
Y1 - 2016/12
N2 - The increase of recent non-recurrent engineering cost (design, mask and test cost) have made large System-on-Chip (SoC) difficult to develop especially with advanced technology. We radically explore an approach for cheap and flexible chip stacking by using Inductive coupling ThruChip Interface (TCI). In order to connect a large number of small chips for building a large scale system, novel chip stacking methods called the linear stacking and staggered stacking are proposed. They enable the system to be extended to x or/and y dimensions, not only to z dimension. Here, a novel chip staking layout, and its deadlock-free routing design for the case using single-core chips and multi-core chips are shown. The network with 256 nodes formed by the proposed stacking improves the latency of 2D mesh by 13.8% and the performance of NAS Parallel Benchmarks by 5.4% on average compared to that of 2D mesh.
AB - The increase of recent non-recurrent engineering cost (design, mask and test cost) have made large System-on-Chip (SoC) difficult to develop especially with advanced technology. We radically explore an approach for cheap and flexible chip stacking by using Inductive coupling ThruChip Interface (TCI). In order to connect a large number of small chips for building a large scale system, novel chip stacking methods called the linear stacking and staggered stacking are proposed. They enable the system to be extended to x or/and y dimensions, not only to z dimension. Here, a novel chip staking layout, and its deadlock-free routing design for the case using single-core chips and multi-core chips are shown. The network with 256 nodes formed by the proposed stacking improves the latency of 2D mesh by 13.8% and the performance of NAS Parallel Benchmarks by 5.4% on average compared to that of 2D mesh.
KW - Inductive coupling interconnect
KW - Interconnection network
KW - Network on chip
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U2 - 10.1587/transinf.2016PAP0033
DO - 10.1587/transinf.2016PAP0033
M3 - Article
AN - SCOPUS:84999233543
SN - 0916-8532
VL - E99D
SP - 2871
EP - 2880
JO - IEICE Transactions on Information and Systems
JF - IEICE Transactions on Information and Systems
IS - 12
ER -