TY - GEN
T1 - On-chip decentralized routers with balanced pipelines for avoiding interconnect bottleneck
AU - Yasudo, Ryota
AU - Matsutani, Hiroki
AU - Koibuchi, Michihiro
AU - Amano, Hideharu
AU - Nakamura, Tadao
N1 - Funding Information:
This work was partially supported by JSPS KAKENHI S #2522002. The authors also would like to thank to the VDEC Tokyo with Synopsys for EDA tools, and STMicroelectronics for its cooperation.
Publisher Copyright:
Copyright 2015 ACM.
PY - 2015/9/28
Y1 - 2015/9/28
N2 - Technology scaling makes designers face difficulties dealing with wire delay of long global interconnects, especially for high-radix networks. In this context, we propose decentralization of on-chip packet routers. A decentralized router consists of submodules, each of which has particular functionality and they are scattered on a link, thereby long wires are segmented. Our starting point is from a conventional router architecture, and we illustrate four case studies to generalize our proposal. We also propose a new buffer design and how to balance pipelines of a router. A proof-of-concept is shown in 28-nm process technology. Our results demonstrate that the decentralization of an on-chip router enables Link Traversal (LT) stages to be eliminated, and the critical path delay is improved by up to 45% with the reduced area compared with a conventional router. As technology advances, the benefit of the decentralized routers become more substantial in the nano-scale era.
AB - Technology scaling makes designers face difficulties dealing with wire delay of long global interconnects, especially for high-radix networks. In this context, we propose decentralization of on-chip packet routers. A decentralized router consists of submodules, each of which has particular functionality and they are scattered on a link, thereby long wires are segmented. Our starting point is from a conventional router architecture, and we illustrate four case studies to generalize our proposal. We also propose a new buffer design and how to balance pipelines of a router. A proof-of-concept is shown in 28-nm process technology. Our results demonstrate that the decentralization of an on-chip router enables Link Traversal (LT) stages to be eliminated, and the critical path delay is improved by up to 45% with the reduced area compared with a conventional router. As technology advances, the benefit of the decentralized routers become more substantial in the nano-scale era.
KW - Decentralized router
KW - Delay model
KW - Interconnect bottleneck
KW - Interconnection networks
KW - Router architecture
KW - Wire delay
UR - http://www.scopus.com/inward/record.url?scp=84984623441&partnerID=8YFLogxK
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U2 - 10.1145/2786572.2786583
DO - 10.1145/2786572.2786583
M3 - Conference contribution
AN - SCOPUS:84984623441
T3 - Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015
BT - Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015
A2 - Marculescu, Diana
A2 - Ivanov, Andre
A2 - Pande, Partha Pratim
A2 - Flich, Jose
PB - Association for Computing Machinery, Inc
T2 - 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015
Y2 - 28 September 2015 through 30 September 2015
ER -