TY - GEN
T1 - On-chip detection methodology for break-even time of power gated function units
AU - Usami, Kimiyoshi
AU - Goto, Yuya
AU - Matsunaga, Kensaku
AU - Koyama, Satoshi
AU - Ikebuchi, Daisuke
AU - Amano, Hideharu
AU - Nakamura, Hiroshi
PY - 2011/9/19
Y1 - 2011/9/19
N2 - In a fine-grain leakage saving technique to power gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off power switches. To get gain in energy savings, the powered-off period has to be longer than the minimum required time i.e. the break-even time (BET). While effectiveness of BET-aware power-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far. This paper proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure. We applied this methodology to the leakage monitors and a CPU including a power-gated multiplier implemented in 65nm CMOS technology. Results showed that our methodology detects BET at 5%-17% difference from that of the conventional simulation-based off-line technique.
AB - In a fine-grain leakage saving technique to power gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off power switches. To get gain in energy savings, the powered-off period has to be longer than the minimum required time i.e. the break-even time (BET). While effectiveness of BET-aware power-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far. This paper proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure. We applied this methodology to the leakage monitors and a CPU including a power-gated multiplier implemented in 65nm CMOS technology. Results showed that our methodology detects BET at 5%-17% difference from that of the conventional simulation-based off-line technique.
KW - break-even time
KW - leakage monitor
KW - power gating
UR - http://www.scopus.com/inward/record.url?scp=80052766406&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=80052766406&partnerID=8YFLogxK
U2 - 10.1109/ISLPED.2011.5993643
DO - 10.1109/ISLPED.2011.5993643
M3 - Conference contribution
AN - SCOPUS:80052766406
SN - 9781612846590
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
SP - 241
EP - 246
BT - IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
T2 - 17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
Y2 - 1 August 2011 through 3 August 2011
ER -