Abstract
An experimental 640-Gbit/s ATM switching system is described. The switching system is scalable and quasi-non-blocking and uses hardware self-rearrangement in a three-stage network. Hardware implementation results for the switching system are presented. The switching system is fabricated using advanced 0.25-μm CMOS devices, high-density multi-chipmodule (MCM) technology, and optical wavelength-division-multiplexing (WDM) interconnection technology. A scalable 80-Gbit/s switching module is fabricated in combination with a developed scalable-distributed-arbitration technique, and a WDM interconnection system that connects multiple 80-Gbit/s switching modules is developed. Using these components, an experimental 640-Gbit/s switching system is partially constructed. The 640-Gbit/s switching system will be applied to future broadband ATM networks.
Original language | English |
---|---|
Pages (from-to) | 1488-1495 |
Number of pages | 8 |
Journal | IEICE Transactions on Communications |
Volume | E83-B |
Issue number | 7 |
Publication status | Published - 2000 Jan 1 |
Externally published | Yes |
Keywords
- ATM
- Interconnection
- Multi-chip module
- Switch
- WDM
ASJC Scopus subject areas
- Software
- Computer Networks and Communications
- Electrical and Electronic Engineering