Overview of low-power ULSI circuit techniques

The low-power circuit techniques for CMOS ULSIs are surveyed and the methods of compensating for the increased delay at low voltage are investigated. Reducing the load capacitance is the principal area of interest because it contributes to the improvement of both power dissipation and circuit speed. Pass-transistor logic is attracting attention as it requires fewer transistors and exhibits less stray capacitance than conventional CMOS static circuits. Variations in its circuit topology as well as a logic synthesis method are presented and studied. A great deal of research effort has been directed towards studying every portion of LSI circuits. The research achievements are categorized by parameters associated with the source of CMOS power dissipation and power use in a chip.