Performance analysis of multistage ATM Switch with partially shared buffers under nonuniform traffic

The system delay and cell loss probability of a multistage shared buffer ATM switch under nonuniform traffic are analyzed. The analysis is made as follows. First, the cell arrival rate at the output port of the switch is calculated from the output address selectivity parameter. Second, the traffic load is sent to a finite-length shared buffer which is allocated at each stage of the switch. Third, the steady-state probability of the queue length is derived from a Markov state transition diagram. Finally, the delay and cell loss probability for each shared buffer are added at each stage and the system delay and system cell loss probability are obtained for the path to each output port. The system delay and cell loss probability for uniform traffic are compared with those for nonuniform traffic. In nonuniform traffic, there are many hot spots at output ports or there is a traffic imbalance. In this case, the system delay and cell loss probability are higher at hot spots which have high traffic intensity compared with other ports. We also show that system delay and cell loss probability are higher at output ports which share buffers with hot spots. We show the influences of hot spots on the other ports.