Performance, cost, and power evaluations of on-chip network topologies in FPGAs

On-chip interconnection network has been used to connect a large number of modules in reconfigurable systems, such as FPGAs. The network topology is a crucial factor that affects the performance, cost, and power consumption of the system, and various network topologies have been proposed so far. To reveal cost- and powerefficient on-chip network structure in the reconfigurable systems, in this paper, we first estimate the performance of 2D-mesh, 2D-torus, Fat-Trees, Spidergon, Concentrated mesh, and Flattened Butterfly by using a network simulator. Then, these topologies are synthesized, placed, and routed by using the Xilinx ISE in order to show the number of slices required and power consumption for each topology. Based on the evaluation results, the performanceper- cost and the performance-per-power of these network topologies are compared. We discuss the pros and cons of the high-radix topologies, such as Concentrated mesh and Flattened Butterfly, when they are used in FPGAs. We also show that the high radix topologies are suitable to FPGAs, because of their relatively small area overhead and short hop count.