TY - GEN
T1 - Performance degradation by deactivated cores in 2-D mesh NoCs
AU - Fujiwara, Ikki
AU - Koibuchi, Michihiro
AU - Matsutani, Hiroki
N1 - Copyright:
Copyright 2014 Elsevier B.V., All rights reserved.
PY - 2013
Y1 - 2013
N2 - Chip MultiProcessors (CMPs) will have dark silicon or frequently deactivated areas in a chip, as technology continues to scale down, due to power dissipation. In this work we estimate the influences of deactivated cores on performance of network-on-chips (NoCs). Even when a chip has a two-dimensional mesh topology, a deactivated core that includes an on-chip router makes topology irregular. We thus assume that a topology-agnostic deadlock-free routing is used with a moderate number of virtual channels in such CMPs. Thorough cycle-accurate network simulations of a 2-D mesh NoC, we found that (1) indeed a deactivated core degrades the performance to some extent in terms of throughput, but (2) latency is not increased or even reduced when a deactivated core is located in the corner of a mesh. Hence, we recommend choosing a corner core for deactivation to maintain the performance of NoCs.
AB - Chip MultiProcessors (CMPs) will have dark silicon or frequently deactivated areas in a chip, as technology continues to scale down, due to power dissipation. In this work we estimate the influences of deactivated cores on performance of network-on-chips (NoCs). Even when a chip has a two-dimensional mesh topology, a deactivated core that includes an on-chip router makes topology irregular. We thus assume that a topology-agnostic deadlock-free routing is used with a moderate number of virtual channels in such CMPs. Thorough cycle-accurate network simulations of a 2-D mesh NoC, we found that (1) indeed a deactivated core degrades the performance to some extent in terms of throughput, but (2) latency is not increased or even reduced when a deactivated core is located in the corner of a mesh. Hence, we recommend choosing a corner core for deactivation to maintain the performance of NoCs.
KW - Darksilicon
KW - Network-on-Chip
KW - Systems on chip
UR - http://www.scopus.com/inward/record.url?scp=84892667427&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84892667427&partnerID=8YFLogxK
U2 - 10.1109/MCSoC.2013.13
DO - 10.1109/MCSoC.2013.13
M3 - Conference contribution
AN - SCOPUS:84892667427
SN - 9780768550862
T3 - Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013
SP - 25
EP - 30
BT - Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013
PB - IEEE Computer Society
T2 - 2013 IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013
Y2 - 26 September 2013 through 28 September 2013
ER -