Performance improvement by stress memorization technique in trigate silicon nanowire MOSFETs

Masumi Saitoh; Yukio Nakabayashi; Kensuke Ota; Ken Uchida; Toshinori Numata

doi:10.1109/LED.2011.2171315

Performance improvement by stress memorization technique in trigate silicon nanowire MOSFETs

Masumi Saitoh, Yukio Nakabayashi, Kensuke Ota, Ken Uchida, Toshinori Numata

Research output: Contribution to journal › Article › peer-review

12 Citations (Scopus)

Abstract

We achieved significant on-current improvement in trigate silicon nanowire transistors by applying stress memorization technique (SMT). We found that the performance improvement by SMT in 110-oriented nanowire nFETs is caused by both the mobility improvement due to vertical compressive strain and the parasitic resistance reduction due to positive fixed charges at the gate edge induced by SMT process. Mobility increase ratio by SMT increases with reducing the nanowire width due to the enhanced strain. Although both the mobility and the parasitic resistance are degraded by SMT in pFETs, much larger performance improvement in nFETs leads to the improvement of total CMOS performance by SMT.

Original language	English
Article number	6072236
Pages (from-to)	8-10
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	33
Issue number	1
DOIs	https://doi.org/10.1109/LED.2011.2171315
Publication status	Published - 2012 Jan
Externally published	Yes

Keywords

Mobility
nanowire transistor
parasitic resistance
stress memorization technique (SMT)
trigate

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/LED.2011.2171315

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title = "Performance improvement by stress memorization technique in trigate silicon nanowire MOSFETs",

abstract = "We achieved significant on-current improvement in trigate silicon nanowire transistors by applying stress memorization technique (SMT). We found that the performance improvement by SMT in 110-oriented nanowire nFETs is caused by both the mobility improvement due to vertical compressive strain and the parasitic resistance reduction due to positive fixed charges at the gate edge induced by SMT process. Mobility increase ratio by SMT increases with reducing the nanowire width due to the enhanced strain. Although both the mobility and the parasitic resistance are degraded by SMT in pFETs, much larger performance improvement in nFETs leads to the improvement of total CMOS performance by SMT.",

keywords = "Mobility, nanowire transistor, parasitic resistance, stress memorization technique (SMT), trigate",

author = "Masumi Saitoh and Yukio Nakabayashi and Kensuke Ota and Ken Uchida and Toshinori Numata",

note = "Funding Information: Manuscript received September 18, 2011; accepted October 3, 2011. Date of publication November 8, 2011; date of current version December 23, 2011. This work was supported in part by NEDO{\textquoteright}s Development of Nanoelectronic Device Technology. The review of this letter was arranged by Editor C. Bulucea.",

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AU - Ota, Kensuke

AU - Uchida, Ken

AU - Numata, Toshinori

N1 - Funding Information: Manuscript received September 18, 2011; accepted October 3, 2011. Date of publication November 8, 2011; date of current version December 23, 2011. This work was supported in part by NEDO’s Development of Nanoelectronic Device Technology. The review of this letter was arranged by Editor C. Bulucea.

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N2 - We achieved significant on-current improvement in trigate silicon nanowire transistors by applying stress memorization technique (SMT). We found that the performance improvement by SMT in 110-oriented nanowire nFETs is caused by both the mobility improvement due to vertical compressive strain and the parasitic resistance reduction due to positive fixed charges at the gate edge induced by SMT process. Mobility increase ratio by SMT increases with reducing the nanowire width due to the enhanced strain. Although both the mobility and the parasitic resistance are degraded by SMT in pFETs, much larger performance improvement in nFETs leads to the improvement of total CMOS performance by SMT.

AB - We achieved significant on-current improvement in trigate silicon nanowire transistors by applying stress memorization technique (SMT). We found that the performance improvement by SMT in 110-oriented nanowire nFETs is caused by both the mobility improvement due to vertical compressive strain and the parasitic resistance reduction due to positive fixed charges at the gate edge induced by SMT process. Mobility increase ratio by SMT increases with reducing the nanowire width due to the enhanced strain. Although both the mobility and the parasitic resistance are degraded by SMT in pFETs, much larger performance improvement in nFETs leads to the improvement of total CMOS performance by SMT.

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Performance improvement by stress memorization technique in trigate silicon nanowire MOSFETs

Abstract

Keywords

ASJC Scopus subject areas

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