Performance, variability and reliability of silicon tri-gate nanowire MOSFETs

Masumi Saitoh, Kensuke Ota, Chika Tanaka, Yukio Nakabayashi, Ken Uchida, Toshinori Numata

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

We systematically study short-channel performance, threshold voltage variability, and negative bias temperature instability in silicon tri-gate nanowire transistors (NW Tr.). By introducing epi S/D with thin gate spacer, on-current of NW Tr. is significantly improved for the same off-current thanks to the parasitic resistance (R SD) reduction. <100>-oriented NW channel further improves on-current as compared to <110> NW channel. In Pelgrom plot of σV th of NW Tr., there exists a universal line whose A vt is smaller than planar Tr. due to gate grain alignment. Deviation of the narrowest Tr. from σV th universal line is eliminated by suppressing R SD. Enhanced degradation by negative bias temperature stress in narrow NW Tr. can be attributed to the electric field concentration at the NW corner.

Original languageEnglish
Title of host publication2012 IEEE International Reliability Physics Symposium, IRPS 2012
Pages6A.3.1-6A.3.6
DOIs
Publication statusPublished - 2012
Externally publishedYes
Event2012 IEEE International Reliability Physics Symposium, IRPS 2012 - Anaheim, CA, United States
Duration: 2012 Apr 152012 Apr 19

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Other

Other2012 IEEE International Reliability Physics Symposium, IRPS 2012
Country/TerritoryUnited States
CityAnaheim, CA
Period12/4/1512/4/19

Keywords

  • nanowire
  • negative bias temperature instability
  • parasitic resistance
  • tri-gate
  • variability

ASJC Scopus subject areas

  • General Engineering

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