PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators

Kentaro Yoshioka; Yosuke Toyama; Koichiro Ban; Daisuke Yashima; Shigeru Maya; Akihide Sai; Kohei Onizuka

doi:10.1109/VLSIC.2018.8502291

PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators

Kentaro Yoshioka, Yosuke Toyama, Koichiro Ban, Daisuke Yashima, Shigeru Maya, Akihide Sai, Kohei Onizuka

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

PhaseMAC (PMAC), a phase domain Gated-Ring-Oscillator (GRO) based 8bit MAC circuit, is proposed to minimize both area and power consumption of deep learning accelerators. PMAC composes of only digital cells and consumes significantly smaller power than standard digital designs, owing to its efficient analog accumulation nature. It occupies 26.6 times smaller area than conventional analog designs, which is competitive to digital MAC circuits. PMAC achieves a peak efficiency of 14 TOPS/W, which is best reported and 48% higher than conventional arts. Results in anomaly detection tasks are demonstrated, which is the hottest application in the industrial IoT scene.

Original language	English
Title of host publication	2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	263-264
Number of pages	2
ISBN (Electronic)	9781538667002
DOIs	https://doi.org/10.1109/VLSIC.2018.8502291
Publication status	Published - 2018 Oct 22
Externally published	Yes
Event	32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 - Honolulu, United States Duration: 2018 Jun 18 → 2018 Jun 22

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2018-June

Other

Other	32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
Country/Territory	United States
City	Honolulu
Period	18/6/18 → 18/6/22

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/VLSIC.2018.8502291

Cite this

Yoshioka, K., Toyama, Y., Ban, K., Yashima, D., Maya, S., Sai, A., & Onizuka, K. (2018). PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators. In 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 (pp. 263-264). Article 8502291 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2018.8502291

PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators. / Yoshioka, Kentaro; Toyama, Yosuke; Ban, Koichiro et al.
2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 263-264 8502291 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yoshioka, K, Toyama, Y, Ban, K, Yashima, D, Maya, S, Sai, A & Onizuka, K 2018, PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators. in 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018., 8502291, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2018-June, Institute of Electrical and Electronics Engineers Inc., pp. 263-264, 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018, Honolulu, United States, 18/6/18. https://doi.org/10.1109/VLSIC.2018.8502291

Yoshioka K, Toyama Y, Ban K, Yashima D, Maya S, Sai A et al. PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators. In 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 263-264. 8502291. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2018.8502291

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abstract = "PhaseMAC (PMAC), a phase domain Gated-Ring-Oscillator (GRO) based 8bit MAC circuit, is proposed to minimize both area and power consumption of deep learning accelerators. PMAC composes of only digital cells and consumes significantly smaller power than standard digital designs, owing to its efficient analog accumulation nature. It occupies 26.6 times smaller area than conventional analog designs, which is competitive to digital MAC circuits. PMAC achieves a peak efficiency of 14 TOPS/W, which is best reported and 48% higher than conventional arts. Results in anomaly detection tasks are demonstrated, which is the hottest application in the industrial IoT scene.",

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AB - PhaseMAC (PMAC), a phase domain Gated-Ring-Oscillator (GRO) based 8bit MAC circuit, is proposed to minimize both area and power consumption of deep learning accelerators. PMAC composes of only digital cells and consumes significantly smaller power than standard digital designs, owing to its efficient analog accumulation nature. It occupies 26.6 times smaller area than conventional analog designs, which is competitive to digital MAC circuits. PMAC achieves a peak efficiency of 14 TOPS/W, which is best reported and 48% higher than conventional arts. Results in anomaly detection tasks are demonstrated, which is the hottest application in the industrial IoT scene.

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PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators

Abstract

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