Physical understanding of Vth and Idsat variations in (110) CMOSFETs

Masumi Saitoh; Nobuaki Yasutake; Yukio Nakabayashi; Ken Uchida; Toshinori Numata

Physical understanding of V_th and I_dsat variations in (110) CMOSFETs

Masumi Saitoh, Nobuaki Yasutake, Yukio Nakabayashi, Ken Uchida, Toshinori Numata

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, the first systematic study of V_th variations (σV_th) and I_dsat variations (σI _dsat) in (110) n/pMOSFETs is presented. σV_th in (110) n/pFETs with high channel dose are larger than (100) n/pFETs. It is found that the variations of B ion channeling, B-induced interface traps, and As-induced interface fixed charges enhance σV_th in (110) n/pFETs. Steep B profile and moderate P doping into the surface are desirable to minimize σV_th in (110) FETs. We also found that σI _dsat is determined by both σV_th and the degree of velocity saturation. σI_dsat of scaled (110) CMOS can be lowered compared to (100) CMOS by the optimum channel impurity design.

Original language	English
Title of host publication	2009 Symposium on VLSI Technology, VLSIT 2009
Pages	114-115
Number of pages	2
Publication status	Published - 2009
Externally published	Yes
Event	2009 Symposium on VLSI Technology, VLSIT 2009 - Kyoto, Japan Duration: 2009 Jun 16 → 2009 Jun 18

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Other

Other	2009 Symposium on VLSI Technology, VLSIT 2009
Country/Territory	Japan
City	Kyoto
Period	09/6/16 → 09/6/18

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

@inproceedings{80a232448b83435b94b7ad59aa2cd604,

title = "Physical understanding of Vth and Idsat variations in (110) CMOSFETs",

abstract = "In this paper, the first systematic study of Vth variations (σVth) and Idsat variations (σI dsat) in (110) n/pMOSFETs is presented. σVth in (110) n/pFETs with high channel dose are larger than (100) n/pFETs. It is found that the variations of B ion channeling, B-induced interface traps, and As-induced interface fixed charges enhance σVth in (110) n/pFETs. Steep B profile and moderate P doping into the surface are desirable to minimize σVth in (110) FETs. We also found that σI dsat is determined by both σVth and the degree of velocity saturation. σIdsat of scaled (110) CMOS can be lowered compared to (100) CMOS by the optimum channel impurity design.",

author = "Masumi Saitoh and Nobuaki Yasutake and Yukio Nakabayashi and Ken Uchida and Toshinori Numata",

year = "2009",

language = "English",

isbn = "9784863480094",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

pages = "114--115",

booktitle = "2009 Symposium on VLSI Technology, VLSIT 2009",

note = "2009 Symposium on VLSI Technology, VLSIT 2009 ; Conference date: 16-06-2009 Through 18-06-2009",

}

TY - GEN

T1 - Physical understanding of Vth and Idsat variations in (110) CMOSFETs

AU - Saitoh, Masumi

AU - Yasutake, Nobuaki

AU - Nakabayashi, Yukio

AU - Uchida, Ken

AU - Numata, Toshinori

PY - 2009

Y1 - 2009

N2 - In this paper, the first systematic study of Vth variations (σVth) and Idsat variations (σI dsat) in (110) n/pMOSFETs is presented. σVth in (110) n/pFETs with high channel dose are larger than (100) n/pFETs. It is found that the variations of B ion channeling, B-induced interface traps, and As-induced interface fixed charges enhance σVth in (110) n/pFETs. Steep B profile and moderate P doping into the surface are desirable to minimize σVth in (110) FETs. We also found that σI dsat is determined by both σVth and the degree of velocity saturation. σIdsat of scaled (110) CMOS can be lowered compared to (100) CMOS by the optimum channel impurity design.

AB - In this paper, the first systematic study of Vth variations (σVth) and Idsat variations (σI dsat) in (110) n/pMOSFETs is presented. σVth in (110) n/pFETs with high channel dose are larger than (100) n/pFETs. It is found that the variations of B ion channeling, B-induced interface traps, and As-induced interface fixed charges enhance σVth in (110) n/pFETs. Steep B profile and moderate P doping into the surface are desirable to minimize σVth in (110) FETs. We also found that σI dsat is determined by both σVth and the degree of velocity saturation. σIdsat of scaled (110) CMOS can be lowered compared to (100) CMOS by the optimum channel impurity design.

UR - http://www.scopus.com/inward/record.url?scp=71049114717&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=71049114717&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:71049114717

SN - 9784863480094

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 114

EP - 115

BT - 2009 Symposium on VLSI Technology, VLSIT 2009

T2 - 2009 Symposium on VLSI Technology, VLSIT 2009

Y2 - 16 June 2009 through 18 June 2009

ER -