Although low power consumption is a significant advantage of FPGA clusters, almost no power analyses with real systems have been reported. This study reports the detailed power consumption analyses of two FPGA clusters, namely, M-KUBOS and FiC, with power measurement tools and real applications. In both clusters, the type of logic design shells determines the base power consumption. For building clusters, the power for node communication links is mainly determined by the number of activated links and not influenced by the number of actually used links. Therefore, applying the link aggregation technique does not affect the power consumption. Increasing the clock frequency of the application logic mildly increases the power consumption. The obtained results suggest that the best way to reduce the total power consumption of an FPGA cluster and improve its performance is to use the minimum number of links for the application, apply link aggregation, and aggressively increase the clock frequency.