TY - GEN
T1 - Prototyping on using a DIMM slot as a high-performance I/O interface
AU - Tanabe, Noboru
AU - Hamada, Yoshihiro
AU - Mitsuhashi, Akihiro
AU - Nakajo, Hironori
AU - Yamamoto, Junji
AU - Imashiro, Hideki
AU - Kudoh, Tomohiro
AU - Amano, Hideharu
N1 - Publisher Copyright:
© 2003 IEEE.
PY - 2003
Y1 - 2003
N2 - DIMMnet-1 is a high-performance network interface for PC clusters that can be directly plugged into the DIMM slot of a PC. In this paper, the architecture, implementation and performance of DIMMnet-1 prototype are mentioned. Experience gained through the prototyping is also reported. In spite of the remaining defectiveness on the implementation, the latency performance is better than that of any other NICs. Although the performance is one-third of the compared to planned bandwidth, two-way sustained bandwidth of DIMMnet-1 on inexpensive PC is not inferior to PCI-X version Infiniband on an expensive server PC. DIMMnet-1 prototype shows the great potential for using a DIMM slot as a high-performance I/O interface on an inexpensive PC.
AB - DIMMnet-1 is a high-performance network interface for PC clusters that can be directly plugged into the DIMM slot of a PC. In this paper, the architecture, implementation and performance of DIMMnet-1 prototype are mentioned. Experience gained through the prototyping is also reported. In spite of the remaining defectiveness on the implementation, the latency performance is better than that of any other NICs. Although the performance is one-third of the compared to planned bandwidth, two-way sustained bandwidth of DIMMnet-1 on inexpensive PC is not inferior to PCI-X version Infiniband on an expensive server PC. DIMMnet-1 prototype shows the great potential for using a DIMM slot as a high-performance I/O interface on an inexpensive PC.
UR - http://www.scopus.com/inward/record.url?scp=77949591897&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77949591897&partnerID=8YFLogxK
U2 - 10.1109/IWIA.2003.1262788
DO - 10.1109/IWIA.2003.1262788
M3 - Conference contribution
AN - SCOPUS:77949591897
T3 - Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems
SP - 108
EP - 116
BT - Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2003
A2 - Veidenbaum, Alex
A2 - Joe, Kazuki
PB - IEEE Computer Society
T2 - Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2003
Y2 - 27 July 2003
ER -