TY - GEN
T1 - Proximity inter-chip communication
AU - Kuroda, Tadahiro
PY - 2006/1/1
Y1 - 2006/1/1
N2 - A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm. The total layout area is 2mm2 in 0.18μm. CMOS and the chip thickness is 10μm. 4-phase TDMA reduces crosstalk and the BER is <10-12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver.
AB - A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm. The total layout area is 2mm2 in 0.18μm. CMOS and the chip thickness is 10μm. 4-phase TDMA reduces crosstalk and the BER is <10-12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver.
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U2 - 10.1109/ICSICT.2006.306462
DO - 10.1109/ICSICT.2006.306462
M3 - Conference contribution
AN - SCOPUS:34547358274
SN - 1424401615
SN - 9781424401611
T3 - ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
SP - 1841
EP - 1844
BT - ICSICT-2006
PB - IEEE Computer Society
T2 - ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology
Y2 - 23 October 2006 through 26 October 2006
ER -