TY - GEN
T1 - QECOOL
T2 - 58th ACM/IEEE Design Automation Conference, DAC 2021
AU - Ueno, Yosuke
AU - Kondo, Masaaki
AU - Tanaka, Masamitsu
AU - Suzuki, Yasunari
AU - Tabuchi, Yutaka
N1 - Funding Information:
ACKNOWLEDGEMENTS This work was supported by JST Mirai Program Grant Number JPMJMI18E1, JST CREST Grant Number JPMJCR18K1, JST PRESTO Grant Number JPMJPR1916, JST ERATO Grant Number JPMJER1601, and MEXT Quantum Leap Flagship Program Grant Numbers JPMXS0120319794, JPMXS0118068682.
Publisher Copyright:
© 2021 IEEE.
PY - 2021/12/5
Y1 - 2021/12/5
N2 - Due to the low error tolerance of a qubit, detecting and correcting errors on it is essential for fault-tolerant quantum computing. Surface code (SC) associated with its decoding algorithm is one of the most promising quantum error correction (QEC) methods. QEC needs to be very power-efficient since the power budget is limited inside of a dilution refrigerator for superconducting qubits by which one of the most successful quantum computers (QCs) is built. In this paper, we propose an online-QEC algorithm and its hardware implementation with SFQ based superconducting digital circuits. We design a key building block of the proposed hardware with an SFQ cell library and evaluate it by the SPICE-level simulation. Each logic element is composed of about 3000 Josephson junctions and power consumption is about 2.78 μW when operating with 2 GHz clock frequency which meets the required decoding speed. Our decoder is simulated on a quantum error simulator for code distances 5 to 13 and achieves a 1.0% accuracy threshold.
AB - Due to the low error tolerance of a qubit, detecting and correcting errors on it is essential for fault-tolerant quantum computing. Surface code (SC) associated with its decoding algorithm is one of the most promising quantum error correction (QEC) methods. QEC needs to be very power-efficient since the power budget is limited inside of a dilution refrigerator for superconducting qubits by which one of the most successful quantum computers (QCs) is built. In this paper, we propose an online-QEC algorithm and its hardware implementation with SFQ based superconducting digital circuits. We design a key building block of the proposed hardware with an SFQ cell library and evaluate it by the SPICE-level simulation. Each logic element is composed of about 3000 Josephson junctions and power consumption is about 2.78 μW when operating with 2 GHz clock frequency which meets the required decoding speed. Our decoder is simulated on a quantum error simulator for code distances 5 to 13 and achieves a 1.0% accuracy threshold.
KW - Quantum Error Correction
KW - SFQ logic
UR - http://www.scopus.com/inward/record.url?scp=85119419073&partnerID=8YFLogxK
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U2 - 10.1109/DAC18074.2021.9586326
DO - 10.1109/DAC18074.2021.9586326
M3 - Conference contribution
AN - SCOPUS:85119419073
T3 - Proceedings - Design Automation Conference
SP - 451
EP - 456
BT - 2021 58th ACM/IEEE Design Automation Conference, DAC 2021
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 5 December 2021 through 9 December 2021
ER -